library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity logic is port(
clk : in std_logic;
PWM1 : in std_logic;
PWM1_out : out std_logic;
PWM1_low_out : out std_logic
);
end logic;
architecture logicar of logic is
signal delay : std_logic_vector(8 downto 0);
begin
process(delay,clk)
begin
if(clk'event and clk ='1')then
delay(0) <= PWM1;
delay(1) <= delay(0);
delay(2) <= delay(1);
end if;
if delay(0) = '0' then
PWM1_out <= delay(2);
PWM1_low_out <= not delay(0);
elsif delay(0) = '1' then
PWM1_out <= delay(0);
PWM1_low_out <= not delay(2);
else
PWM1_out <= '1';
PWM1_low_out <= '1';
end if;
end process;
end logicar;
Мертвое время соответственно 2 периода clk