Оно ворчит
Warning (10762): Verilog HDL Case Statement warning at comdec1.v(103): can't check case statement for completeness because the case expression has too many possible states

Warning (10766): Verilog HDL warning at comdec1.v(103): ignoring full_case attribute on case statement with explicit default

Аналогично, если как у Вас, сделать.

Если убрать default, то вместо второго пишет
Warning (10208): Verilog HDL Case Statement warning: implemented Verilog HDL full_case synthesis attribute at comdec1.v(103) -- differences between design synthesis and simulation may occur

При этом все чудесно симулится......