module leds (clock, nReset, in, out);
input clock, nReset;
input [3:0] in;
output reg [23:0] out;

reg [4:0] cnt_a;
reg [1:0] cnt_b;
always @(posedge clock or negedge nReset)
  if (!nReset)
    cnt_a <= 5'd0;
  else if (cnt_a == 5'd23)
    cnt_a <= 5'd0;
  else
    cnt_a <= cnt_a + 1'b1;
always @(posedge clock or negedge nReset)
  if (!nReset)
    cnt_b <= 2'b00;
  else if (cnt_b[1])
    cnt_b <= 2'b00;
  else
    cnt_b <= cnt_b + 1'b1;
always @(posedge clock)
  begin
    if (in[0]) out <= 24'h000001 << cnt_a;    /* rotate left by 1 */
    if (in[1]) out <= 24'h800000 >> cnt_a;     /* rotate right by 1 */
    if (in[2]) out <= 24'h0000FF << {cnt_b, 3'h0 }; /* rotate left by 8 */
    if (in[3]) out <= 24'hFF0000 >> {cnt_b, 3'h0 }; /* rotate right by 8 */
  end
endmodule