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library IEEE;
use IEEE.std_logic_1164.all;
entity shft_reg8 is
port (
CLK : in std_logic;
LOAD : in std_logic;
DATA : in std_logic_vector(7 downto 0);
SO : out std_logic
);
end entity;
architecture shft_reg_arch of shft_reg8 is
signal TEMP_SO : std_logic_vector(7 downto 0);
begin
process(CLK)
begin
if rising_edge(CLK) then
if LOAD = '1' then
TEMP_SO <= DATA;
else
TEMP_SO <= '0' & TEMP_SO(7 downto 1);
end if;
end if;
end process;
SO <= TEMP_SO(0);
end architecture;
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