|
|
module enable_wr
(
input global_clk,
input [7:0] data_a, data_b, data_c, data_d,
input clk_a, clk_b, clk_c, clk_d,
output reg [7:0] out_a, out_b, out_c, out_d,
output reg int_a, int_b, int_c, int_d
);
reg [2:0] shift_rg_a;
reg [2:0] shift_rg_b;
reg [2:0] shift_rg_c;
reg [2:0] shift_rg_d;
always @ (posedge global_clk)
begin
shift_rg_a <= {shift_rg_a[1:0], clk_a};
shift_rg_b <= {shift_rg_b[1:0], clk_b};
shift_rg_c <= {shift_rg_c[1:0], clk_c};
shift_rg_d <= {shift_rg_d[1:0], clk_d};
if (~shift_rg_a[2] & shift_rg_a[1]) out_a <= data_a;
if (~shift_rg_b[2] & shift_rg_b[1]) out_b <= data_b;
if (~shift_rg_c[2] & shift_rg_c[1]) out_c <= data_c;
if (~shift_rg_d[2] & shift_rg_d[1]) out_d <= data_d;
int_a <= ~shift_rg_a[2] & shift_rg_a[1];
int_b <= ~shift_rg_b[2] & shift_rg_b[1];
int_c <= ~shift_rg_c[2] & shift_rg_c[1];
int_d <= ~shift_rg_d[2] & shift_rg_d[1];
end
endmodule
|
|
