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# Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
# // ModelSim SE 6.1b Sep 8 2005
# //
# // Copyright Mentor Graphics Corporation 2005
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do {test_clock.tdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
# -- Compiling module clock
# -- Compiling module glbl
#
# Top level modules:
# clock
# glbl
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
# -- Compiling module test_clock
#
# Top level modules:
# test_clock
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L simprims_ver -lib work -t 1ps +maxdelays test_clock glbl
# Loading work.test_clock
# Loading work.clock
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_OPAD
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_OBUF
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_IPAD
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_BUF
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_BUFGMUX
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_INV
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_DCM
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.x_dcm_clock_divide_by_2
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.x_dcm_maximum_period_check
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.x_dcm_clock_lost
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_GT
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.GT_SWIFT
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.GT_SWIFT_BIT
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_LUT4
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_ONE
# Loading C:\Xilinx\verilog\mti_se\simprims_ver.X_ZERO
# Loading work.glbl
# ** Warning: (vsim-PLI-3003) C:/Xilinx/verilog/mti_se/simprims_ver/simprims_ver_SmartWrapper_source.v(18339): [TOFD] - System task or function '$lm_model' is not defined.
# Region: /test_clock/UUT/\module1/GT_CUSTOM_INST\/gt_swift_1/I1
# ** Warning: (vsim-3017) test_clock.tfw(62): [TFMPC] - Too few port connections. Expected 14, found 12.
# Region: /test_clock/UUT
# ** Warning: (vsim-3722) test_clock.tfw(62): [TFMPC] - Missing connection for port 'RXP'.
# ** Warning: (vsim-3722) test_clock.tfw(62): [TFMPC] - Missing connection for port 'RXN'.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /test_clock File: test_clock.tfw
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# No errors or warnings.
# Break at test_clock.tfw line 73
# Simulation Breakpoint: Break at test_clock.tfw line 73
# MACRO ./test_clock.tdo PAUSED at line 16
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