// 4 to 1 multiplexer design with case construct
// input [1:0] SEL;
// input A, B, C, D;
// output MUX_OUT;
// reg MUX_OUT;always @(SEL or A or B or C or D)
begin
case (SEL)
2'b00 : MUX_OUT = A;
2'b01 : MUX_OUT = B;
2'b10 : MUX_OUT = C;
2'b11 : MUX_OUT = D;
default : MUX_OUT = 0;
endcase
end
ИЛИ
// 4 to 1 multiplexer design with tri-state construct
// input [3:0] SEL;
// input A, B, C, D;
// output MUX_OUT;
// wire MUX_OUT;
assign MUX_OUT = SEL[3] ? A :1'bz;
assign MUX_OUT = SEL[2] ? B :1'bz;
assign MUX_OUT = SEL[1] ? C :1'bz;
assign MUX_OUT = SEL[0] ? D :1'bz;
