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How Quartus II (v.2.2 SP2) can be directed to accommodate two logic functions in same logic cells of ACEX1K if one function uses CASCADE primitive and another function uses CARRY primitive to derive their a bit per function outputs? The example below exposes the problems. The Quartus result is 33 LC and functions have been realized on different sets of LCs. The MAX+PLUS II (v.10.2) result is 17 LC and functions have been implemented on the same set of LCs.
Sincerely,
Andrey
TITLE "Comparator of two 16 bits digits with A>B and A==B outputs";
-- ************************************************************************************************************
-- Comparator of two 16 bits digits with A>B and A==B outputs.
-- To minimize area, Carry and Cascade buffers in same Logics Cells are extensive used.
--
-- Specification:
--
-- Input data A and B width: 16 bits
-- Outputs: A > B and A == B
--
-- ************************************************************************************************************
SUBDESIGN cmp_cc
(
dataa[15..0] : INPUT; -- Data A to compare
datab[15..0] : INPUT; -- Data B to compare
AeB : OUTPUT; -- A == B
AgB : OUTPUT; -- A > B
)
VARIABLE
a_eq_b[15..0] : NODE; -- Output of Cascade buffers to derive A == B
a_gr_b[15..0] : NODE; -- Output of Carry buffers to derive A > B
BEGIN
FOR i IN 1 TO 14 GENERATE
-- A == B generation
a_eq_b[15 - i] = CASCADE( (dataa[15 - i] !$ datab[15 - i]) & a_eq_b[15 - 1 - i] );
-- A > B generation
a_gr_b[15 - i] = CARRY( dataa[15 - i] & !datab[15 - i]
# (dataa[15 - i] !$ datab[15 - i]) & a_gr_b[15 - 1 - i] );
END GENERATE;
-- A == B the first and the final stages
a_eq_b[0] = CASCADE(dataa[0] !$ datab[0]);
a_eq_b[15] = (dataa[15] !$ datab[15]) & a_eq_b[14];
AeB = a_eq_b[15];
-- A > B the first and the final stages
a_gr_b[0] = CARRY(dataa[0] & !datab[0]);
a_gr_b[15] = CARRY( dataa[15] & !datab[15]
# (dataa[15] !$ datab[15]) & a_gr_b[14] );
AgB = a_gr_b[15];
END;
------------ ОТВЕТ САПОРТА
Andrey.
The CARRY_SUM primitive is a two-input, two-output primitive that designates the carry-out and sum-out logic for a function. The cout port of the primitive acts as the carry-in for the next element of the carry chain. The carry function implements fast carry-chain logic for functions such as adders and counters.
When you use a CARRY_SUM primitive, you must observe the following rules:
The cout port of the CARRY_SUM primitive can feed one or two cones of logic. If the CARRY_SUM primitive feeds two cones of logic, then one and only one of the cones of logic must be buffered by another CARRY_SUM primitive. In this case, both cones of logic are implemented in the same logic cell. You must follow this rule to tie down the sum and carry-out functions for the first stage of an adder or counter.
A cone of logic that feeds the cin port of a CARRY_SUM primitive can have up to two inputs. A third input is allowed only if it is a CARRY_SUM input, or a qfeedback from the register.
The cout port of the CARRY_SUM primitive cannot feed an OUTPUT pin.
The cin port of the CARRY_SUM primitive cannot be fed by an INPUT pin.
The cout port of two different CARRY_SUM primitives cannot feed the same gate.
Regards,
Amit
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