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Согласен. Чем это хуже?
module counter(clk, out_clk);
input clk;
output out_clk;
reg [3:0] ct_a;
reg ct_b;
always @(posedge clk) begin
if (ct_a == 9) ct_a <= 4'h0;
else ct_a <= ct_a + 1'b1;
if (ct_a == 9) ct_b <= ct_b + 1'b1; end
assign out_clk = ct_b;
endmodule
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