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Вот типа бреда
module dff_ea
(
input r_n,
input s_n,
input aload,
input adata,
output reg out
);
wire clk;
wire input_d;
wire ena;
assign clk = 1'b1;
assign input_d = 1'b1;
assign ena = 1'b1;
always@ (posedge clk or negedge r_n or negedge s_n or posedge aload)
begin
if (r_n == 1'b0) out <= 1'b0;
else if (s_n == 1'b0) out <= 1'b1;
else if (aload) out <= adata;
else if (ena) out <= input_d;
end
endmodule
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