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■ Core Features
—Integrated Intel XScale® Core
—ARM* V5T Instruction Set
—ARM V5E DSP Extensions
—400 MHz and 600 MHz
—Write Buffer, Write-back Cache
■ PCI Bus Interface
—PCI Local Bus Specification, Rev. 2.2
compliant
—PCI-X Addendum to the PCI Local Bus
Specification, Rev. 1.0a
—64-bit/66 MHz Operation in PCI Mode
—64-bit/133 MHz Operation in PCI-X
Mode
—Support 32-bit PCI Initiators and Targets
—Four Split Read Requests as Initiator
—Eight Split Read Requests as Target
—64-bit Addressing Support
■ Memory Controller
—PC200 Double Data Rate (DDR) SDRAM
—Up to 1 Gbyte of 64-bit DDR SDRAM
—Up to 512 Mbytes of 32-bit DDR SDRAM
—Single-bit Error Correction, Multi-bit Support (ECC)
—1024-byte Posted Memory Write Queue
—40- and 72-bit wide Memory Interface
■ Address Translation Unit
—2 Kbyte or 4 Kbyte Outbound Read Queue
—4 Kbyte Outbound Write Queue
—4 Kbyte Inbound Read and Write Queue
—Connects Internal Bus to PCI/PCI-X Bus
■ DMA Controller
—Two Independent Channels Connected
to Internal Bus
—Up to 1064 Mbytes/s Burst Support in PCI-X Mode
—Up to 1600 Mbytes/s Burst Support for Internal Bus
—Two 1-Kbyte Queues in Ch-0 and Ch-1
—232 Addressing Range on Internal Bus Interface
—264 Addressing Range on PCI Interface
■ I2C Bus Interface Units
—Two Separate I2C Units
—Serial Bus
—Master/Slave Capabilities
—System Management Functions
■ Peripheral Performance Monitoring Unit
—One Dedicated Global Time Stamp Counter
—Fourteen Programmable Event Counters
—Three Control/Status Registers
■ Timers
—Two Dual-programmable 32-bit Timers
—Watchdog Timer
■ 544-Ball, Plastic Ball Grid Array (PBGA)
■ Eight General Purpose I/O Pins
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E-mail: 
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