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после запуска на выполнение пункта "simulate post-translate veriloge model", QuestaSim выдала следующее:
# Reading C:/QuestaSim_6.1d/tcl/vsim/pref.tcl
# // QuestaSim 6.1d Jan 23 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do uo_tbw.ndo
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim vlog 6.1d Compiler 2006.01 Jan 23 2006
# -- Compiling module glbl
#
# Top level modules:
# glbl
# QuestaSim vlog 6.1d Compiler 2006.01 Jan 23 2006
# -- Compiling module uo
#
# Top level modules:
# uo
# QuestaSim vlog 6.1d Compiler 2006.01 Jan 23 2006
# -- Compiling module uo_tbw
#
# Top level modules:
# uo_tbw
# vsim -L simprims_ver -lib work -t 1ps uo_tbw glbl
# Loading work.uo_tbw
# Loading work.uo
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_BUF
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_IPAD
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_OPAD
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_CKBUF
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_FF
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_SRL16E
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_XOR2
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_AND2
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_LUT4
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_MUX2
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_ZERO
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_ONE
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_RAMB4_S16
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_SFF
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_LUT2
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_LUT3
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_INV
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_OR2
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.X_TRI
# Loading work.glbl
# ** Error: (vsim-3063) uo_tbw.translate_tfw(75): Port '_56MHz' not found in the connected module (1st connection).
# Region: /uo_tbw/UUT
# ** Error: (vsim-3063) uo_tbw.translate_tfw(75): Port '_4MHz' not found in the connected module (2nd connection).
# Region: /uo_tbw/UUT
# Loading C:\QuestaSim_6.1d\win32/../xilinx/verilog/simprims_ver.ffsrce
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (1st connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (2nd connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (3rd connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (4th connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (5th connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (6th connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Error: (vsim-3389) uo_translate.v(7419): Port '(null)' not found in the connected module (7th connection).
# Region: /uo_tbw/UUT/\U16/BU1417\
# ** Fatal: (vsim-3365) uo_translate.v(7419): Too many port connections. Expected 6, found 13.
# Time: 0 ps Iteration: 0 Instance: /uo_tbw/UUT/\U16/BU1417\ File: C:/Xilinx/verilog/src/simprims/X_FF.v
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./uo_tbw.ndo PAUSED at line 9
проект проходит этапы синтез и имплемент без ощибок. что может быть?
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