Отправлено -=Sergei=- 31 мая 2002 г. 15:02 В ответ на: Век живи, век учись и ...: отправлено Vallav 31 мая 2002 г. 11:20

library IEEE;
use IEEE.std_logic_1164.all;

entity test is
port (
x1: in STD_LOGIC;
x2: in STD_LOGIC;
x3: in STD_LOGIC;
nx1: out STD_LOGIC;
nx2: out STD_LOGIC;
nx3: out STD_LOGIC
);
end test;

architecture test of test is
signal a: std_logic;
signal b: std_logic;
signal S1: std_logic;
signal S2: std_logic;
signal S3: std_logic;
signal S4: std_logic;
signal S5: std_logic;
signal S6: std_logic;
signal S7: std_logic;
signal S8: std_logic;

begin

--a=not(x1x2+x1x3+x2x3)
--b=not(a(x1+x2+x3)+x1x2x3)
--S8=ab
--S7=a(x1+x3)(x2+x3)
--S6=a(x1+x2)(x2+x3)
--S5=bx2x3
--S4=a(x1+x2)(x1+x3)
--S3=bx1x3
--S2=bx1x2
--S1=x1x2x3
--not(x1)=S8+S7+S6+S5
--not(x2)=S8+S7+S4+S3
--not(x3)=S8+S6+S4+S2

a <= not( (x1 and x2) or (x1 and x3) or (x2 and x3));
b <= not(a and (x1 or x2 or x3) and x1 and x2 and x3);
S8 <= a and b;
S7 <= a and (x1 or x3) and (x2 or x3);
S6 <= a and (x1 or x2)and(x2 or x3);
S5 <= b and x2 and x3;
S4 <= a and (x1 or x2) and (x1 or x3);
S3 <= b and x1 and x3;
S2 <= b and x1 and x2;
S1 <= x1 and x2 and x3;
nx1 <= S8 or S7 or S6 or S5;
nx2 <= S8 or S7 or S4 or S3;
nx3 <= S8 or S6 or S4 or S2;

end test;

Может ошибся где?

• Таблица (+) — -=Sergei=-   (31.05.2002 15:10, 421 байт)
  • Извиняюсь, обшибся :) — -=Sergei=-   (31.05.2002 16:57, пустое)