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Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
--Library unisim;
--Use unisim.all;
entity GG_CLOCK is
port (
RESET : in std_logic;
CLK_IN : in std_logic;
CLK_OUT: out std_logic;
LOCK : out std_logic
);
attribute syn_blackbox : boolean;
end GG_CLOCK;
architecture RTL of GG_CLOCK is
component IBUF port (I : in std_logic; O : out std_logic); end component;
attribute syn_blackbox of IBUF : component is true;
component IBUFG port (I : in std_logic; O : out std_logic); end component;
attribute syn_blackbox of IBUFG : component is true;
component BUFG port (I : in std_logic; O : out std_logic); end component;
attribute syn_blackbox of BUFG : component is true;
component CLKDLL
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
CLK0 :out std_logic;
CLK90 :out std_logic;
CLK180 :out std_logic;
CLK270 :out std_logic;
CLK2X :out std_logic;
CLKDV :out std_logic;
LOCKED :out std_logic
);
end component;
attribute syn_blackbox of CLKDLL : component is true;
signal CLK_IN_w, RST, RST_b, CLK0_dll, CLK0_g, CLK2X_dll, CLK1X, LOCKED : std_logic;
begin
RST <= not RESET; -- make it active high
rstpad : IBUF port map (I => RST, O => RST_b); -- input clock
clkpad : IBUFG port map (I => CLK_IN, O => CLK_IN_w); -- input clock
dll : CLKDLL port map (
CLKIN => CLK_IN_w,
CLKFB => CLK0_g,
RST => RST_b, -- Virtex DLL
CLK0 => CLK0_dll,
CLK90 => open,
CLK180=> open,
CLK270=> open,
CLK2X => CLK2X_dll,
CLKDV => open,
LOCKED=> LOCKED
);
process(RST, LOCKED, CLK2X_dll)
begin
if ((RST = '1') or (LOCKED = '1')) then
CLK1X <= '0';
elsif rising_edge(CLK2X_dll) then
CLK1X <= not CLK1X;
end if;
end process;
clkg : BUFG port map (I => CLK0_dll, O => CLK0_g);
buf1x: BUFG port map (I => CLK1X, O => CLK_OUT);
LOCK <= LOCKED;
end RTL;
На сайте Xilinx есть application notes о том как правильно подключать DLL (правда для Спартана)
E-mail: 
info@telesys.ru
