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module dwigdat(clk,d,lh,symb);
input [2:0] d;
input clk,lh;
output [7:0] symb;
reg [7:0] symb;
reg [7:0] pos;
reg [1:0] STATE,STATEold;
wire [3:0] byte;
assign byte=lh? pos[7:4]:pos[3:0];
semiseg semiseg1(byte,symb);
/*always @(negedge clk)
case (byte)
0: symb=8'b00000011;
1: symb=8'b10011111;
2: symb=8'b00100101;
3: symb=8'b00001101;
4: symb=8'b10011001;
5: symb=8'b01001001;
6: symb=8'b01000001;
7: symb=8'b00011111;
8: symb=8'b00000001;
9: symb=8'b00001001;
10: symb=8'b00010001;
11: symb=8'b11000001;
12: symb=8'b01100011;
13: symb=8'b10000101;
14: symb=8'b01100001;
15: symb=8'b01110001;
endcase*/
always @(negedge clk)
begin
STATEold=STATE;
end
always @(posedge clk)
case (d)
3'b110 :
begin
STATE=0;
case (STATEold)
1:pos=pos-1;
2:pos=pos+1;
endcase
end
3'b101 :
begin
STATE=1;
case (STATEold)
2:pos=pos-1;
0:pos=pos+1;
endcase
end
3'b011 :
begin
STATE=2;
case (STATEold)
0:pos=pos-1;
1:pos=pos+1;
endcase
end
endcase
//end
endmodule
22222222222222222222
module fepdat(a,b,clk,pwm_up,pwm_dn);
/*
Digital encoder processing.
Inputs a,b - two meanders shifted on 90 grad.
Output pwm_up,pwm_dn - 1us impulse _each_ front of _each_ meanders + 1us impulse between two fronts (in the centre)
clk - in Africa it's known also as Clock.
Front detection.
It exists four different states for inputs "a" and "b" - 00, 01, 11, and 10
Front detection looks on state changes. Every state change indicate level change (front)
on one of nwo inputs. Direction of state changes indicate the direction of rotating.
- ld=0 during one clock indicates the front.
- dir=0 indicates rotation to the right, dir=1 indicates rotation to the left
Impulse generation.
Impulse against the front - impulse_0.
This impulse is generated simply by inverting signal "ld".
- impulse_0=!ld.
Impulse between of two fronts - impulse_1.
The counter "cnt" is reset on each front of input signals and counts farther
until the next front is appeared. (In the case of absence of rotation counter "cnt"
is stopped after achieving state 0ffdH).
On each front the counter "cnt1" is loaded by inverted contents of "cnt" shifted by one
(inverting indicates negation-1 and shifting by one indicates dividing by two).
Then counter "cnt1" counts to the "7ff" (max number).
- impulse_1=1 while cnt1="7ff".
Counter "cnt" stops count in the state "000" to avoid continuous generating of impulses
at the time sensor staying.
*/
input a,b,clk; //clk = 1 MHz
output pwm_up,pwm_dn;
reg [11:0] cnt;
reg [10:0] cnt1;
reg [1:0] state;
wire impulse_0;
wire impulse_1;
reg dir;
wire [1:0] st0,st1,st2,st3;
wire up,dn;
wire [10:0] cntinv;
reg ld;
assign st0=0,st1=1,st2=3,st3=2;
assign up=0,dn=1;
assign pwm_dn=(impulse_0 | impulse_1) & dir;//(dir==up);
assign pwm_up=(impulse_0 | impulse_1) & (!dir);//(dir==dn);
always @(posedge clk)
begin
if (ld==0)
cnt<=0;
else
if (cnt!=12'hffd) cnt<=cnt+1;
end
assign impulse_0=!ld;
lpm_inv lpm_inv1(cnt[11:1],cntinv);defparam lpm_inv1.lpm_width = 11;
always @(posedge clk)
begin
if (ld==0)
cnt1<=cntinv;
else
if (cnt1!=0) cnt1<=cnt1+1;
end
assign impulse_1=cnt1[0]&cnt1[1]&cnt1[2]&cnt1[3]&cnt1[4]&cnt1[5]&cnt1[6]&cnt1[7]&cnt1[8]&cnt1[9]&cnt1[10];
always @(negedge clk)
begin
state<={a,b};
if (state!={a,b}) ld<=0;
else ld<=1;
end
always @(negedge clk)
case (state)
st0: case ({a,b})
st3:dir<=dn;
st1:dir<=up;
endcase
st1: case ({a,b})
st0:dir<=dn;
st2:dir<=up;
endcase
st2: case ({a,b})
st1:dir<=dn;
st3:dir<=up;
endcase
st3: case ({a,b})
st2:dir<=dn;
st0:dir<=up;
endcase
default:;
endcase
endmodule
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