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module fsm2 (x, clk, rst, y);
input x, clk, rst;
output y;
parameter [3:0]
set0 = 4'b0001, hold0 = 4'b0010, hold1 = 4'b1000;
reg [3:0] current_state, next_state;
always @ (posedge clk or posedge rst)
if (rst)
next_state = set0;
else begin
next_state = current_state;
case (current_state)
set0:
next_state = hold0;
hold0:
if (x == 0)
next_state = hold0;
else
next_state = hold1;
hold1:
next_state = set0;
endcase
end
assign y = current_state == hold0;
always @(posedge clk)
current_state = next_state;
endmodule
мое мнение - уроды
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