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module test01(clk, dout);
input clk;
output [16:0] dout;
reg [16:0] VidAddr ;
reg [16:0] iVidAddr ;
assign dout = VidAddr;
always @(negedge clk or posedge clk) begin
if (!clk) begin
VidAddr <= 17'bz;
iVidAddr <= iVidAddr+1;
end
else
VidAddr <= iVidAddr;
end
endmodule
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