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Работающий (и до и после PAR) вариант кода
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fignz is
Port ( clock : in std_logic;
reset : in std_logic;
test : out std_logic);
end fignz;
architecture Behavioral of fignz is
begin
process begin
wait until clock'event and clock='1';
if (reset='0')
then test <= '1';
else test <= '0';
end if;
end process;
end Behavioral;
Используется
WebPack ISE 4.2i wp0.0-синьез
ModelSim XE Starter 5.5e-моделирование
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