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есть проект, простой делитель частоты на 4, сделанный в коре генераторе
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_onentity div4 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKDV_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end div4;architecture BEHAVIORAL of div4 is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND : std_logic_vector (6 downto 0);
signal GND1 : std_logic_vector (15 downto 0);
signal GND2 : std_logic;
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;
component IBUFG
port ( I : in std_logic;
O : out std_logic);
end component;
component DCM_ADV
generic( CLK_FEEDBACK : string := "1X";
CLKDV_DIVIDE : real := 2.000000;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLKIN_PERIOD : real := 0.000000;
CLKOUT_PHASE_SHIFT : string := "NONE";
DCM_AUTOCALIBRATION : boolean := TRUE;
DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := FALSE;
FACTORY_JF : bit_vector := x"F0F0");
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DADDR : in std_logic_vector (6 downto 0);
DI : in std_logic_vector (15 downto 0);
DWE : in std_logic;
DEN : in std_logic;
DCLK : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
DRDY : out std_logic;
DO : out std_logic_vector (15 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;
begin
GND(6 downto 0) <= "0000000";
GND1(15 downto 0) <= "0000000000000000";
GND2 <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000000,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE,
FACTORY_JF => x"F0F0")
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DADDR(6 downto 0)=>GND(6 downto 0),
DCLK=>GND2,
DEN=>GND2,
DI(15 downto 0)=>GND1(15 downto 0),
DWE=>GND2,
PSCLK=>GND2,
PSEN=>GND2,
PSINCDEC=>GND2,
RST=>RST_IN,
CLKDV=>CLKDV_BUF,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open);
end BEHAVIORAL;
В файле ничего не менялось, сответствующий файл констрейнов "пристегнул", синтез в исе проходит на ура, но мапер вылетает с сообщением :
FATAL_ERROR:Portability:PortDynamicLib.c:278:1.20 - dll open of library Сталкивались ли вы с подобным ? если да, то как боролись ?
E-mail:
reason. Process will terminate. To resolve this error, please consult the
Answers Database and other online resources at http://support.xilinx.com. If
you need further assistance, please open a Webcase by clicking on the
"WebCase" link at http://support.xilinx.com
Ответы
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