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Incremental compilation is an optional part of the Quartus II software compilation flow that allows you to reduce total compilation time by 50-70 % by preserving and reusing previous compilation results. Incremental compilation allows you to break your design into physical and logical partitions for synthesis and fitting. Design partitions that have changed between design iterations are recompiled, while unchanged partitions are not recompiled. This preserves the performance of unchanged partitions and reduces compilation time. SignalTap II incremental compilation speeds up the debugging process by allowing you to not have to recompile the design.
Incremental compilation is also useful for achieving timing closure. You can use this feature to apply optimization techniques, such as physical synthesis, to specific design partitions that do not meet timing goals while leaving other partitions untouched.
You can designate any design hierarchy under the top-level entity to be a design partition. Partitions are bound by hierarchical boundaries and therefore cannot be a portion of the logic within a hierarchical block. When you designate a partition, every hierarchical block within the partition becomes part of the same partition. You can create new partitions for hierarchical blocks within an existing partition, in which case the blocks within the new partition are no longer part of the higher-level partition. In the example that follows, the hierarchies speed_ch:speed and time_cnt:time_c are designated as design partitions. Any design instance designated as a design partition is displayed with a partition icon ( ) in the Hierarchy tab of the Project Navigator. Creating a partition prevents the Compiler from performing optimizations across the partition boundaries, thus making incremental compilation possible. Before partitions can be set, you must first perform Analysis & Elaboration on the design to obtain the design hierarchy.
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