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module formir_odin
(
input in_interval, // _____/'''''''\_____
input clk, // '''''''\________/''''''''''''''
output en_wr_a, // _____/''\____________
output en_wr_b,
output en_wr_c
);
reg [1:0] shift_rg;
always @(posedge clk)
begin
shift_rg <= {shift_rg[0], in_interval};
end
assign en_wr_a = shift_rg[0] & ~shift_rg[1];
assign en_wr_b = ~shift_rg[0] & shift_rg[1];
assign en_wr_c = shift_rg[0] ^ shift_rg[1];
endmodule
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