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5.6 8 388 607-bit pseudo-random test sequence
This sequence is primarily intended for error and jitter measurements at bit rates of 34 368, 44 736 and 139 264 kbit/s (see Recommendation O.151 [4]).
The sequence may be generated in a twenty-three-stage shift register whose 18th and 23rd stage outputs are added in a modulo two addition stage, and the result is fed back to the input of the first stage.
– Number of shift register stages 23
– Length of pseudo-random sequence 223 – 1 8 388 607 bits
– Longest sequence of zeros 23 (inverted signal)
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