Отправлено PicoDev2 09 марта 2005 г. 03:24 В ответ на: Если подойдет 1000BASE-T (+) отправлено code_id 08 марта 2005 г. 10:14

как TLK1501 (лучше) ,TLK1201 от TI
Только бы добавить FIFO и CRC, как например, в LSI Logic. ($60)

или:

The GL9711 (GigaCourier™/PHY) is one of Genesys Logic’s GigaCourier™ PCI Express series products. The GL9711 provides the transceiver functions needed to implement a single lane PCI Express device. The GL9711 is compliant with PCI Express Base Specification Rev. 1.0a and the PCI Express PHY Interface Specification Rev. 0.9 defined by Intel. The GL9711 supports Intel’s PHY/MAC interface (PPI) which is defined as a standard interface between Physical Coding Sub-Layer (PCS) and Media Access Controller Sub-Layer (MAC). PCS and MAC together serve as the Physical Layer of the PCI Express system.

The GL9711 supports an effective serial interface speed of 2.5 Gb/s as defined in PCI Express Base Spec Rev1.0a. The transmitter latches 8-bit/16-bit data from TXD[15:0] and encodes it into 10-bit/20-bit using 8B/10B encoding rules. These encoding data are then serialized and transmitted differentially. The receiver collects 10-bit/20-bit input data and decodes it into 8-bit/16-bit parallel data (RXD[15:0]) using 8B/10B decoding rules. The bus width of parallel data (8-bit or 16-bit) is determined by the value of the PBUS8 pin.

The GL9711 supports different power down mode circuits for conditions where the data no longer has to be transmitted. All power states (P0, P0s, P1, and P2) defined in PCI Express PHY Interface Specification are implemented. The GL9711 also provides several loop-back functions for self-test purposes, allowing the functional self-check of the analog transceiver.

PIPE Architecture

The PHY Interface for PCI Express Architecture (PIPE) is defined by Intel® Corporation. The PIPE Architecture defines a standard interface between PCI Express MAC and Physical Coding Sublayer (PCS). The intent of PIPE specification is to accelerate PCI Express endpoint device development. By insulating the high-speed and analog circuitry issue associated with PCI Express, PCI application vendors can minimize the effort to migrate their design into next generation’s PCI Express design.