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Intel preps HyperTransport competitor for Xeon, Itanium CPUs
Posted: 07 Mar 2005
Intel Corp. plans to embedded a memory controller and to use a common high-speed serial interconnect as the processor bus for its Itanium and Xeon server processors starting in 2007, EE Times has learned.
The so-called CSI interconnect will compete with HyperTransport - the fast, low latency processor bus developed by Advanced Micro Devices Inc. and used on its K8-class Opteron and Athlon processors.
AMD made HyperTransport an industry standard interconnect that is now used on a wide variety of chips including network processors from companies such as Broadcom Corp. and PMC-Sierra.
Intel has not yet decided whether it will make CSI an open standard. The final specification for the interconnect is still being hammered out by engineers working with the server CPU design teams, according to a source close to the project.
In their ongoing microprocessor wars, AMD beat Intel on several fronts with its K8 design that became the first 64bit x86 with an embedded memory controller and an industry-standard cache coherent processor bus. Intel caught up last year with the move to 64bits, but it won't be until 2007 that the CPU giant delivers on the other fronts.
Intel has already shipped 2.5 million 64bit x86 systems, said Patrick Gelsinger, general manager of Intel's Digital Enterprise group in a keynote session Tuesday (Mar. 1) at the Intel Developer Forum here. Virtually all Intel's server CPUs will be 64bit enabled by the end of the year, he added.
"The message to the industry is to develop for 64bit systems now," said Gelsinger. Intel has more than caught up with AMD in the 64bit arena, and the two companies are competing head-to-head in rolling out multi-core x86 CPUs. However, Intel still lags AMD in that it lacks an embedded memory controller and standard processor interconnect to create simple multiprocessors servers, said Nathan Brookwood, analyst with Insight64 (Saratoga, Calif.).
"AMD's multi-core approach uses more integration. Conceptually, it gives them greater advantages in 2- and 4-way servers," said Brookwood.
Intel's CSI bus will first appear on the Tukwila, a multi-core version of Intel Itanium CPU set to ship in 2007. The processor will use "many more" than two CPU cores, according to Intel.
By the end of the decade, Intel server CPUs will support up to 32 threads using four processor cores with eight threads each. That would compete with Niagara, a 32-thread server CPU in design at Sun Microsystems.
The CSI bus is also expected to appear in 2007 versions of Intel's x86 Xeon server CPUs, probably including the chip code-named Whitefield.
The CSI bus is optimized for low latency when used as a cache coherent processor bus in four-processor systems. However, it can also be used to link up to 16 CPUs for the high-end X86 systems built by OEMs such as IBM, NEC and Unisys. In addition, CSI will be used without cache coherency as a standard way to link north and south bridge chips in a processor core logic set.
By using a common interconnect as a chip-to-chip link, Intel will be able to develop similar board-level designs and software tools for Itanium and Xeon systems. That could reduce the costs of supporting the two server architectures.
Intel executives faced heated questioning over the future of the Itanium architecture at the Intel Developer Forum. Last spring, Intel announced it would release 64-bit versions of Xeon and Pentium processors to keep up with AMD's K8. At that time, the company said it would focus the Itanium on high-end servers, competing with IBM's Power and Sun Sparc, typically in large symmetric multiprocessing systems.
A number of analysts have questioned the long-term logic of maintaining a separate architecture to compete with Power and Sparc.
- Rick Merritt
EE Times
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