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-- Top level file for a16450P - Parameterized UART
-- In this module, all signals are assertive HIGH
CONSTANT REVISION = "$date: 4/05/99 $ $Revision: 2.1 $ ";
-- I've set the revision at 1.1 to reflect the fix for the
-- scrambled interrupt enables. -Mikep, 8 June 1998
ASSERT REPORT "Compiling Altera MegaCore a16450P Parameterized UART Version 2.1"
SEVERITY INFO;
ASSERT REPORT "Compiling Altera MegaCore a16450P Parameterized UART Version 2.1 %" REVISION
SEVERITY DEBUG;
CONSTANT RBR = 0; -- reggie addresses in like, space, man. I mean, address space
CONSTANT THR = 0;
CONSTANT IER = 1;
CONSTANT IIR = 2;
CONSTANT LCR = 3;
CONSTANT MCR = 4;
CONSTANT LSR = 5;
CONSTANT MSR = 6;
CONSTANT SCR = 7;
CONSTANT DLSB = 8;
CONSTANT DMSB = 9;
-- $Author: pmolson $
% Old includes when the files had meaningful names, before attempting to obfuscate them.
INCLUDE "baudgen.inc";
INCLUDE "busblock.inc";
INCLUDE "interrupt.inc";
INCLUDE "rxserialif.inc";
INCLUDE "tx.inc";
INCLUDE "rx.inc";
INCLUDE "modemif.inc";
%
FUNCTION a16450P00 (clk, mr, din[7..0], divmsb_sel, divlsb_sel, we, divisor_in[15..0])
WITH (divisor_reg, divisor_static_value, generate_baudout)
RETURNS (nbaudout, baudclk_event, divmsb_out[7..0], divlsb_out[7..0], eq0or1);
FUNCTION a16450p10 (mr, clk, cs, a[2..0], ads, rd, wr, din[7..0], rbr[7..0], ier[7..0], iir[7..0], lcr[7..0], mcr[7..0], lsr[7..0], msr[7..0], scr[7..0], dlsb[7..0], dmsb[7..0], drab)
WITH (bypass_areg_on_wr, bypass_areg_on_rd, dout_register_instantiate, rd_lsr_clr_errors, rd_rxreg_clr_DR, rd_iir_hold_iir)
RETURNS (dout[7..0], csout, sel[9..0], write_en, read_en, rd_lsr, rd_rxreg, rdiir_holdiir, datain[7..0]);
FUNCTION a16450P20 (clk, mr, ier_sel, we, din[3..0], intidreg_we, lsr_int, rxdata_int, thre_int, msr_int)
WITH (int_enable_reg, rx_instantiate)
RETURNS (inten_dout[7..0], intid_dout[2..0], intr);
FUNCTION a16450P60 (mr, clk, sel_mcr, wr, rd, din[4..0], sel_msr, frommodem[7..4])
RETURNS (mcrdout[4..0], msr_int, msrdout[7..0]);
FUNCTION a16450P40 (disable_clearTHRE, eq0or1, mr, clk, din[7..0], sel0, sel2, we, rd, baudclk_event, word_lngth[1..0], parity_en, stopbit2_en, parity_even, stick_par, break)
WITH (ld_thr_clears_thre, rd_iir_clears_int)
RETURNS (sout, thre_int, lsr[7..5] );
FUNCTION a16450P50 (mr, clk, sin, eq0or1, word_lngth[1..0], parity_even, parity_en, stick_par, rxbaudclk, rd_lsr, rd_rxreg)
RETURNS (data_out[7..0], lsr[4..0], lsr_int );
FUNCTION a16450P30 (clk, mr, ext_sin, tx_sout, loopback_en, ext_rclk_in, baudclk_event)
WITH (rclk_source_internal, tx_instantiate, rx_instantiate)
RETURNS (rxbaudclk, sin, sout);
FUNCTION a16450P99 (clk, mr, in, en)
WITH (RISE_OR_FALL)
RETURNS (out);
-- a16450P99 is a parametized edge detector.
-- WARNING: Comments such as the long-winded diatribe below could well be obsolete by now!
-- With numeric register parameters, setting a parameter value of zero
-- causes the register to be instantiated. It then functions as usual in
-- the 16450 UART.
-- On the other hand, setting the parameter to non-zero means that the register
-- won't be instantiated. Instead, it's value will be set as static nodes
-- in the design.
-- Thus, if you want the normal divisor register, and wish to change baud rate
-- during in-system operation, set the divisor PARAMETER to zero. Do not
-- confuse this step with loading a value of zero during in-system operation.
-- On the other hand, if you kb"0"w at design time that your baud rate is fixed
-- relative to the system clock ( the clk input ) then you can set the parameter
-- to the appropriate value. This will result in logic cell savings as the
-- register won't be instantiated.
-- Similar comments apply to the LCR register and its associated parameter. If
-- you want the settings to be static rather than programmable (referring to
-- in-system operation), then set the parameter to the register value you desire.
-- Line Control Register (LCR)
-- bit[1..0]: 00 = 5 bit, 01 = 6, 10 = 7, 11 = 8 bit data
-- bit[2] : 0 = one stop bit, 1 = two stop bits (one-and-a-half b"0"t supported)
-- bit[3] : 1 = parity enabled
-- bit[4] : 1 = parity even
-- bit[5] : 1 = stick parity - I don't have a clue what this does
-- bit[6] : 1 = break - forces break (low) on the sout output
-- bit[7] : divisor register access bit (drab). Need to deal with separately!
-- If LCR parameter is set to b"0"n-zero, it won't be instantiated. In this case
-- the internal signal is
---------------------------------------------------------------------------------------
-- Parameters Section
---------------------------------------------------------------------------------------
parameters
(
tx_instantiate = 1,
rx_instantiate = 1,
divisor_reg = b"01", -- 01= instantiate, 10= input, 1X = static
divisor_static_value = H"0001",
baudout_generate = 1, -- if 0, saves a few LCells
rclk_source_internal = 1, -- highly recommended ! b"0" need to connect nbaudout to ext_rclk if you select "INTERNAL"
LCR_bits_1 = b"00000000", --msb of bit-by-bit code 1=static, and overrides lsb code
LCR_bits_0 = b"11111111", --lsb 1= instantiate, 0 = input.
LCR_static_value = b"00000000",
int_enable_reg = h"0" , -- 0 means instantiate, non-zero is the static value. HEX!
modem_I/F_instantiate = 1 , -- modem status/control registers and associated logic
loopback_bit = 1, -- instantiate (1) or input (0), only relevant if modem NOT instantiated
bypass_a/cs_reg_on_rd = 0, -- change latency of micro bus timing
bypass_a/cs_reg_on_wr = 0,-- if "b"1"", bypasses the address and cs registers
dout_register_instantiate = 1, -- dout data from output mux is registered (enabled by rd & cs).
scratchreg_instantiate = 1 -- optional scratchpad register
);
---------------------------------------------------------------------------------------
-- Error messages and info
---------------------------------------------------------------------------------------
-- check if the user has requested parity_enable bit static, with value zero
CONSTANT parstaticoff = ( ((LCR_bits_1 & b"00001000") DIV 8) AND
NOT ((LCR_bits_0 & b"00001000") DIV 8) AND
NOT ( (LCR_static_value & b"00001000") DIV 8) );
CONSTANT parstaticon = ( ((LCR_bits_1 & b"00001000") DIV 8) AND
NOT ((LCR_bits_0 & b"00001000") DIV 8) AND
( (LCR_static_value & b"00001000") DIV 8) );
-- figure out the chosen setting for the DRAB bit, so we can give him some feedback
CONSTANT drabstat = ( (LCR_bits_1 & b"10000000") DIV 128); -- static
CONSTANT drabinst = ( (LCR_bits_0 & b"10000000") DIV 128); -- 1=inst, 0 = inp
CONSTANT divstat = ( (divisor_reg & b"10" ) DIV 2); -- static divisor
CONSTANT lcrallinst = (255 - LCR_bits_0 ); -- suppress some info if he's got a totally default LCR
CONSTANT lcrnonestat = (LCR_bits_1 - 0 ) ;
-- messages about the important bits
ASSERT (tx_instantiate == 1) # (tx_instantiate == 0)
REPORT "Parameter tx_instantiate values: 1 or 0."
SEVERITY ERROR;
ASSERT (rx_instantiate == 1) # (rx_instantiate == 0)
REPORT "Parameter rx_instantiate values: 1 or 0."
SEVERITY ERROR;
ASSERT (rclk_source_internal == 1) # (rclk_source_internal == 0)
REPORT "Parameter rx_source_internal values: 1 or 0."
SEVERITY ERROR;
ASSERT (baudout_generate == 1) # (baudout_generate == 0)
REPORT "Parameter baudout_generate values: 1 or 0"
SEVERITY ERROR;
--LCR messages
ASSERT (LCR_bits_1 < 256) --# (LCR_bits_0 == 0)
REPORT "Parameter LCR_bits_1 is % - value must be an 8-bit number." LCR_bits_0
SEVERITY ERROR;
ASSERT (LCR_bits_0 < 256) --# (LCR_bits_0 == 0)
REPORT "Parameter LCR_bits_0 is % - value must be an 8-bit number." LCR_bits_0
SEVERITY ERROR;
ASSERT NOT ( (lcrallinst == 0) AND (lcrnonestat == 0) ) -- the default LCR setting
REPORT "All LCR bits will be instantiated as normal. The lcr_in[] inputs will be redundant."
SEVERITY INFO;
ASSERT (LCR_bits_1 == 0)
REPORT "Some or all LCR bits have been set to static. For these bits the register will not be instantiated, and the lcr_in[] input will be redundant."
SEVERITY INFO;
ASSERT (parstaticoff != 1)
REPORT "Parity has been set to static, disabled."
SEVERITY INFO;
ASSERT (parstaticon != 1)
REPORT "Parity has been set to static, enabled."
SEVERITY INFO;
-- detailed warnings about DRAB, because DRAB is so special...
ASSERT NOT( drabstat == 0 AND drabinst == 1 AND NOT divstat AND NOT ((lcrallinst == 0) AND (lcrnonestat == 0)) ) -- warning irrelevant if divisor reg is static
REPORT "Divisor register access bit ( LCR[7] ) will be instantiated."
SEVERITY INFO;
ASSERT NOT(drabstat == 0 AND drabinst == 0 AND NOT divstat)
REPORT "Divisor register access bit ( LCR[7] ) will be driven by the lcr_in[7] input port."
SEVERITY INFO;
ASSERT NOT(drabstat == 1 AND NOT divstat )
REPORT "Divisor register access bit ( LCR[7] ) has been set to static. You will not be able to vary baud rate at run time."
SEVERITY INFO;
-- modem messages
ASSERT (modem_I/F_instantiate == 1) # (modem_I/F_instantiate == 0)
REPORT "Parameter modem_I/F_instantiate values: 1 or 0"
SEVERITY ERROR;
ASSERT (loopback_bit == 1) # (loopback_bit == 0)
REPORT "Parameter loopback_bit values: 1 or 0"
SEVERITY ERROR;
ASSERT (modem_I/F_instantiate != 1)
REPORT "Modem interface module will be instantiated. Loopback_en input will be redundant."
SEVERITY INFO;
ASSERT NOT ((modem_I/F_instantiate == 0 ) AND (loopback_bit == 1 ))
REPORT "Modem interface module will not be instantiated, but loopback enable bit ( MCR[4] ) will be instantiated. The ndcd, nri, ndsr, ncts inputs will be redundant."
SEVERITY INFO;
ASSERT NOT ((modem_I/F_instantiate == 0 ) AND (loopback_bit == 0 ))
REPORT "Modem interface module will not be instantiated, but loopback enable bit ( MCR[4] ) will be driven by the loopback_en input port. The ndcd, nri, ndsr, ncts inputs will be redundant."
SEVERITY INFO;
-- bus baloney - but this is now checked in the busblock module
%
ASSERT (bypass_a/cs_reg_on_rd == 1) # (bypass_a/cs_reg_on_rd == 0)
REPORT "Parameter bypass_a/cs_reg_on_rd values: 1 or 0."
SEVERITY ERROR;
ASSERT (bypass_a/cs_reg_on_wr == 1) # (bypass_a/cs_reg_on_wr == 0)
REPORT "Parameter bypass_a/cs_reg_on_wr values: 1 or 0."
SEVERITY ERROR;
ASSERT (dout_register_instantiate == 1) # (dout_register_instantiate == 0)
REPORT "Parameter dout_register values: 1 or 0."
SEVERITY ERROR;
%
-- and then whether he has scratched on the scratch, or scratched the itch FOR a scratch
ASSERT (scratchreg_instantiate == 1 ) # (scratchreg_instantiate == 0 )
REPORT "Parameter scratchreg_instantiate values: 1 or 0."
SEVERITY ERROR;
ASSERT (scratchreg_instantiate != 0 )
REPORT "Scratchpad register will not be instantiated."
SEVERITY INFO;
--must have either tx or rx, otherwise this whole exercise was pretty pointless
ASSERT (rx_instantiate == 1) # (tx_instantiate == 1 )
REPORT "Parameters rx_instantiate, tx_instantiate cannot both be 0."
SEVERITY ERROR;
---------------------------------------------------------------------------------------
-- Subdesign Section: Top-level Ports
---------------------------------------------------------------------------------------
subdesign a16450p
(
-- the microprocessor bus side:
mr :INPUT; -- a HIGH resets/sets internal flops appropriately
clk :INPUT; -- the master clock - all internal logic is sync to this
cs :INPUT = GND; -- assertive HIGH
a[2..0] :INPUT = GND;
ads :INPUT = GND; -- assertive HIGH
rd :INPUT = GND; -- assertive HIGH
wr :INPUT = GND; -- assertive HIGH
din[7..0] :INPUT = GND;
dout[7..0] :OUTPUT;
intr :OUTPUT; -- interrupt to microprocessor
csout :OUTPUT;
-- the serial interface side:
sin :INPUT = VCC; -- serial data input
ext_rclk :INPUT = GND; -- external rclk source - usually not necessary
sout :OUTPUT; -- serial data output
nbaudout :OUTPUT; -- redundant, not used internally - for compatibility
-- special inputs for when blow-awayable things are not instantiated
loopback_en :INPUT = GND; -- in case MCR is blown away, this was bit 4
lcr_in[7..0] :INPUT = GND; --optional lcr values
divisor_in[15..0] :INPUT = GND; -- can we set this to 0001??
-- optional modem interface:
ndcd :INPUT = GND; -- complement goes to MSR7 (invert done in modemif module, b"0"t here)
nri :INPUT = GND; -- to MSR6
ndsr :INPUT = GND; -- to MSR5
ncts :INPUT = GND; -- to MSR4
nout2 :OUTPUT; -- from MCR3, gets inverted in modem module
nout1 :OUTPUT; -- from MCR2
nrts :OUTPUT; -- from MCR1
ndtr :OUTPUT; -- from MCR0
--testport[7..0] :OUTPUT; -- test only
)
---------------------------------------------------------------------------------------
-- Variable Section
---------------------------------------------------------------------------------------
VARIABLE
junkndcd, junknri, junkndsr, junkncts :node; --warning suppression if modem i/f blown away
junkloopen :node;
baud :a16450P00 WITH (divisor_reg = divisor_reg, divisor_static_value = divisor_static_value,baudout_generate = baudout_generate);
busblock :a16450P10 WITH (bypass_areg_on_wr = bypass_a/cs_reg_on_wr, bypass_areg_on_rd = bypass_a/cs_reg_on_rd, dout_register_instantiate = dout_register_instantiate ); --bus I/F, signal con, decode, outmux
int :a16450P20 WITH (int_enable_reg = int_enable_reg, rx_instantiate = rx_instantiate);
serialif :a16450P30 WITH (rclk_source_internal = rclk_source_internal, tx_instantiate = tx_instantiate, rx_instantiate = rx_instantiate); -- takes care of loopback and rclk choice (parameter)
IF (tx_instantiate == 1 ) GENERATE
IF (parstaticoff == 1) GENERATE
transmitter :a16450P40 WITH (parity_on = 0, ld_thr_clears_thre = "ASSERT_EDGE", rd_iir_clears_int = "DEASSERT_EDGE");
ELSE GENERATE
transmitter :a16450P40 WITH (parity_on = 1, ld_thr_clears_thre = "ASSERT_EDGE", rd_iir_clears_int = "DEASSERT_EDGE");
END GENERATE ;
END GENERATE;
IF (rx_instantiate == 1 ) GENERATE
IF (parstaticoff == 1) GENERATE
receiver :a16450P50 WITH (parity_on = 0);
ELSE GENERATE
receiver :a16450P50 WITH (parity_on = 1);
END GENERATE;
END GENERATE;
IF (modem_I/F_instantiate == 1) GENERATE
modemblock :a16450P60;
END GENERATE;
IF ((modem_I/F_instantiate == 0) AND (loopback_bit == 1)) GENERATE
loopreg :DFFE;
END GENERATE;
IF (scratchreg_instantiate == 1) GENERATE
scratch[7..0] :DFFE;
END GENERATE;
lcrreg[7..0] :DFFE ; -- always instantiate
loopnode :node ; -- comes from MCR[4] or input
lcrnode[7..0] :node ; -- for the LCR reg, or whatever replaces it
--these nodes make the LCR section more understandable
lcrsel0[7..0] :node ; -- used for LCR bit-by-bit. Selects instantiate or input
lcrsel1[7..0] :node ; -- selects static, overrides the above
muxout[7..0] :node ; --
-- PM Modif begin
eq0or1 : dff ;
-- PM Modif end
---------------------------------------------------------------------------------------
-- End of Variable Section
---------------------------------------------------------------------------------------
BEGIN
junkndcd = junkndcd & ndcd;
junknri = junknri & nri;
junkndsr = junkndsr & ndsr;
junkncts = junkncts & ncts;
junkloopen = junkloopen & loopback_en;
--testport[] = lcrnode[];
--connect signals that drive the primary outputs
dout[7..0] = busblock.dout[7..0];
intr = int.intr;
sout = serialif.sout; --final sout register & loop control is in the serial I/F
nbaudout = baud.nbaudout; -- this was forced to one in baudgen, if param disables it
csout = busblock.csout ; --user can use to enable external logic, generate ddis signal
-- see modem section for modem primary I/O
--inputs to bus interface block that are primary inputs
busblock.(mr,clk) = (mr, clk);
busblock.cs = cs;
busblock.a[] = a[];
busblock.ads = ads;
busblock.rd = rd;
busblock.wr = wr;
busblock.drab = lcrnode[7];
busblock.din[] = din[];
--inputs to bus interface that are to the mux - these are the register outputs
--see the appropriate sections for reggies that are blow-awayable
busblock.ier[7..0] = int.inten_dout[];
busblock.iir[7..0] = (GND, GND, GND, GND, GND, int.intid_dout[2..0]);
busblock.lcr[7..0] = lcrnode[];
busblock.dlsb[7..0] = baud.divlsb_out[];
busblock.dmsb[7..0] = baud.divmsb_out[];
--inputs to serial interface
serialif.clk = clk;
serialif.mr = mr;
serialif.ext_sin = sin;
serialif.loopback_en = loopnode; -- this node is always here in one form or another
serialif.ext_rclk_in = ext_rclk;
serialif.baudclk_event = baud.baudclk_event;
--receiver inputs
-- see separate section
--transmitter inputs
-- see separate section
--baud generator inputs
baud.(mr,clk) = (mr, clk);
-- PM Modif begin
eq0or1.(clk, clrn) = (clk, !mr);
eq0or1 = baud.eq0or1;
-- PM Modif end
baud.din[] = busblock.datain[];
baud.divmsb_sel = busblock.sel[DMSB];
baud.divlsb_sel = busblock.sel[DLSB];
baud.we = busblock.write_en;
baud.divisor_in[] = divisor_in[];
--interrupt thing inputs
int.(mr, clk) = (mr, clk);
int.ier_sel = busblock.sel[IER]; --IER is reg # 1
int.we = busblock.write_en;
int.din[3..0] = busblock.datain[3..0]; -- so we can write the IER
int.intidreg_we = !busblock.rdiir_holdiir; -- disables it from loading while reading
IF (rx_instantiate == 1) GENERATE
int.lsr_int = receiver.lsr_int;
int.rxdata_int = receiver.lsr[0] ; -- just the DR bit of LSR
ELSE GENERATE
int.lsr_int = GND;
int.rxdata_int = GND ; -- just the DR bit of LSR
END GENERATE;
IF (tx_instantiate == 1) GENERATE
int.thre_int = transmitter.thre_int;
ELSE GENERATE
int.thre_int = GND;
END GENERATE;
IF (modem_I/F_instantiate == 1) GENERATE
int.msr_int = modemblock.msr_int ;
END GENERATE;
IF (modem_I/F_instantiate == 0) GENERATE
int.msr_int = GND ;
END GENERATE;
---------------------------------------------------------------------------
--Scratchpad - a straightforward blow-awayable register
---------------------------------------------------------------------------
% These ASSERTS are now at the top in the main assert section
ASSERT (scratchreg_instantiate != 0 )
REPORT "Scratchpad register will not be instantiated."
SEVERITY INFO;
%
IF (scratchreg_instantiate == 1 ) GENERATE
busblock.scr[] = scratch[].q;
scratch[].(clrn, clk ) = (!mr, clk);
scratch[].ena = busblock.sel[SCR] & busblock.write_en ;
scratch[].d = busblock.datain[] ;
ELSE GENERATE
busblock.scr[] = GND; -- feed GND to the bus mux inputs otherwise it bitches
END GENERATE;
---------------------------------------------------------------------------
--Modem block
---------------------------------------------------------------------------
%ASSERT (modem_I/F_instantiate != 0 ) -- no need for this as it's repeated further up.
REPORT "Modem interface module will not be instantiated."
SEVERITY INFO;
%
IF (modem_I/F_instantiate == 1) GENERATE
--primary outputs driven by outputs of modem chunk
(nout2, nout1, nrts, ndtr) = !modemblock.mcrdout[3..0] ; -- inverted
--other things driven by outputs of modemblock
busblock.mcr[7..0] = (GND,GND,GND, modemblock.mcrdout[4..0]); -- not inverted
--(modemblock.msr_int SEE INTERRUPT SECTION)
busblock.msr[7..0] = modemblock.msrdout[7..0];
loopnode = modemblock.mcrdout[4] ;
--modem chunk's inputs
modemblock.(mr, clk) = (mr, clk);
modemblock.sel_mcr = busblock.sel[MCR];
modemblock.sel_msr = busblock.sel[MSR];
modemblock.wr = busblock.write_en;
modemblock.rd = busblock.read_en;
modemblock.din[4..0] = busblock.datain[4..0];
modemblock.frommodem[7..4] = (ndcd, nri, ndsr, ncts);
ELSE GENERATE
(nout2, nout1, nrts, ndtr) = (GND,GND,GND,GND);
busblock.mcr[7..0] = GND;
busblock.msr[7..0] = GND;
END GENERATE;
IF ((modem_I/F_instantiate == 0 ) AND (loopback_bit == 1 )) GENERATE
loopreg.(clrn, clk) = (!mr, clk);
loopreg.ena = busblock.sel[MCR] & busblock.write_en;
loopreg.d = busblock.datain[4]; --this is bit position 4 on bus
loopnode = loopreg.q;
END GENERATE;
IF ((modem_I/F_instantiate == 0) AND (loopback_bit == 0)) GENERATE
loopnode = loopback_en; -- route straight to input of same name
END GENERATE;
---------------------------------------------------------------------------
--Receiver block
---------------------------------------------------------------------------
ASSERT (rx_instantiate != 0 )
REPORT "Receiver module will not be instantiated."
SEVERITY INFO;
IF (rx_instantiate == 1 ) GENERATE
-- things what depend on receiver's outputs
busblock.rbr[7..0] = receiver.data_out[];
busblock.lsr[4..0] = receiver.lsr[4..0];
-- PM Modif begin
receiver.eq0or1 = eq0or1;
-- PM Modif end
-- connect receiver inputs
receiver.rxbaudclk = serialif.rxbaudclk; -- either internal or external, per parameter
receiver.sin = serialif.sin; -- either int or ext, per loopback_en bit.
receiver.(mr, clk) = (mr, clk);
receiver.word_lngth[1..0] = lcrnode[1..0];
receiver.parity_even = lcrnode[4];
receiver.parity_en = lcrnode[3];
receiver.stick_par = lcrnode[5];
receiver.rd_lsr = busblock.rd_lsr; --busblock provides signal conditioning
receiver.rd_rxreg = busblock.rd_rxreg; --ditto
ELSE GENERATE
busblock.rbr[7..0] = GND;
busblock.lsr[4..0] = GND;
END GENERATE;
---------------------------------------------------------------------------
--Transmitter block
---------------------------------------------------------------------------
ASSERT (tx_instantiate != 0 )
REPORT "Transmitter module will not be instantiated."
SEVERITY INFO;
IF (tx_instantiate == 1 ) GENERATE
-- things what depend on transmitter's outputs being there in a time of need
serialif.tx_sout = transmitter.sout;
busblock.lsr[7..5] = transmitter.lsr[7..5]; -- tx provides the upper lsr bits
-- connect transmitter inputs
-- MP Modif (7 April 1999) begin
transmitter.disable_clearTHRE = int.intid_dout[2];
-- MP Modif end
-- PM Modif begin
transmitter.eq0or1 = eq0or1;
-- PM Modif end
transmitter.mr = mr;
transmitter.clk = clk;
transmitter.din[] = busblock.datain[];
transmitter.sel0 = busblock.sel[THR];
transmitter.sel2 = busblock.sel[IIR]; -- reading IIR clears THRE-based interrupt
transmitter.we = busblock.write_en;
transmitter.rd = busblock.read_en;
transmitter.baudclk_event = baud.baudclk_event;
transmitter.word_lngth[1..0] = lcrnode[1..0];
transmitter.parity_en = lcrnode[3];
transmitter.stick_par = lcrnode[5];
transmitter.stopbit2_en = lcrnode[2];
transmitter.parity_even = lcrnode[4];
transmitter.break = lcrnode[6];
ELSE GENERATE
serialif.tx_sout = VCC; -- just drive a high
busblock.lsr[7..5] = (GND); -- drive default values for idle tx
END GENERATE;
---------------------------------------------------------------------------
--LCR
---------------------------------------------------------------------------
lcrreg[].(clrn, clk ) = (!mr, clk);
lcrreg[7..0].d = busblock.datain[7..0];
lcrreg[7..0].ena = busblock.sel[LCR] & busblock.write_en ;
lcrsel0[] = LCR_bits_0; --dummy assignments so we can treat as group
lcrsel1[] = LCR_bits_1;
muxout[] = (lcrsel0[] & lcrreg[].q) OR (!lcrsel0[] & lcr_in[] );
lcrnode[] = (lcrsel1[] & LCR_static_value) OR (!lcrsel1[] & muxout[] );
-- Now, if we could embed graphics in tdf files, we wouldn't have to do crap
-- like this:
-- LCR_static_value * ___
-- ___ | | \
-- | \ |_____| |
-- lcrreg.q ____| | | |_____ lcrnode
-- | |_____________| |
-- lcr_in ______| | |___/
-- |___/ |
-- | |
-- lcrsel0 _______| |
-- |
-- lcrsel1 _________________________|
END;
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$author : $
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$log : $
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