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The system must assert RST# during power up or in the event of a power failure. In order
to minimize possible voltage contention between 5V and 3.3V parts, RST# must be asserted
as soon as possible during the power up sequence. Figure 4-11 shows a worst case assertion
of RST# asynchronously following the "power good" signal.33 After RST# is asserted, PCI
components must asynchronously disable (float) their outputs but are not considered reset
until both Trst and Trst-clk parameters have been met. The first rising edge of RST# after
power-on for any device must be no less than Tpvrh after all the power supply voltages are
within their specified limits for that device. If RST# is asserted while the power supply
voltages remain within their specified limits, the minimum pulse width of RST# is Trst.
Figure 4-11 shows RST# signal timing.
The system must guarantee that the bus remains in the idle state for a minimum time delay
following the deassertion of RST# to a device before the system will permit the first
assertion of FRAME#. This time delay is included in Table 4-6 as Reset High to First
FRAME# assertion (Trhff). If a device requires longer than the specified time (Trhff) after
the deassertion of RST# before it is ready to participate in the bus signaling protocol, then
the device's state machines must remain in the reset state until all of the following are
simultaneously true:
RST# is deasserted.
The device is ready to participate in the bus signaling protocol.
The bus is in the idle state.
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