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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity x is
port(
outdata: out integer;
indata: in std_logic_vector(31 downto 0)
);
end x;
architecture y of probe is
begin
process (indata)
begin
outdata <= conv_integer(indata);
end process;
end y;
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