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architecture rtl of MyEntity is
-- declare black box component
component SRL16 is
port(
D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component;
attribute box_type of SRL16 : component is "primitive";
-- synthesis translate_off
-- simulaton models
-- associate black box interface with simulation model
for all: SRL16 use
entity UNISIM.SRL16(SRL16_V);
-- synthesis translate_on
begin
...
mapSRL16: SRL16
port map(
D => D,
CLK => Clk,
A0 => '0',
A1 => '0',
A2 => '1',
A3 => '1',
Q => Q
);
...
end rtl;
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