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"The Catapult C Synthesis tool offers a mature, second-generation algorithmic synthesis environment which automatically generates error-free RTL from untimed C++ up to 20x faster than traditional manual methods. Using pure, untimed C++ to describe functional intent, designers move up to a more productive abstraction level for designing complex ASIC or FPGA hardware typically found in next-generation, compute-intensive applications. The tool’s advanced “what if” analysis allows hardware designers to fully explore the micro-architecture
and interface design space yielding high performance hardware which rivals hand-coded design
quality. Catapult C unites two distinct domains, system-level design and hardware design, and
when combined with Mentor Graphics ModelSim simulation tools, creates the key cornerstone
for next-generation electronic system level (ESL) design."
E-mail: info@telesys.ru