Отправлено Romario 09 августа 2004 г. 14:38 В ответ на: Может мы говорим о разных буферах отправлено _pavel 09 августа 2004 г. 14:19

экспериментировал с памятью ACEX. в Описании на VHDL пока слабоват
так что просьба не ругать за стиль:)
данный фифо работал.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.all;
ENTITY pulse_ent IS
PORT (
	 clk    :   in     Std_logic;
         sin    :   in 	   Std_logic;
	 pulse  :   out	   Std_logic);
END pulse_ent;

ARCHITECTURE pulse_rtl OF pulse_ent IS
signal q, qq: std_logic;
BEGIN
process(sin, clk)
begin
if (sin = '0') then
q  <= '0';
qq <= '0';
elsif (rising_edge(clk)) then
q  <= '1';
qq <=  q;
end if;
end process;
pulse <= q and (not qq);
END pulse_rtl;

------------------------------------
LIBRARY ieee;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.all;

ENTITY fiforw IS
PORT (
		
	     fclk :	IN     Std_logic;   -- sys_clk
	     srd  :	IN     Std_logic;   -- для чтения нужен перепад из 0 в 1
	     swr  :	IN     Std_logic;   -- для записи нужен перепад из 0 в 1
	  wdata	  :     IN     STD_LOGIC_VECTOR (7 DOWNTO 0);
	  rdata	  :     OUT    STD_LOGIC_VECTOR (7 DOWNTO 0)
	 );
END fiforw;

ARCHITECTURE rw_fifo OF fiforw IS

component pulse 
PORT (
	     clk    :   in     Std_logic;
	     sin    :	in     Std_logic;
	     pulse  :	out    Std_logic);
END component;
for all: pulse use entity work.pulse_ent;

component fifo
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq		: IN STD_LOGIC ;
		rdreq		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		full		: OUT STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		usedw		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
end component;
SIGNAL 	 		wrreq_sig,fifo_clk,fifo_clkr,fifo_clkw	: STD_LOGIC ;
SIGNAL 	 		wres,rres,rdreq_sig	: STD_LOGIC ;
SIGNAL 	 		full_sig: STD_LOGIC ;
SIGNAL 	 		empty_sig	: STD_LOGIC ;
SIGNAL 	 		usedw_sig	: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL 	 		rstate,
			wstate   : STD_LOGIC_VECTOR (1 DOWNTO 0);

BEGIN
fifo_inst:component  fifo PORT MAP (
		data	 => wdata	,
		wrreq	 => wrreq_sig,
		rdreq	 => rdreq_sig,
		clock	 => fifo_clk,
		q	 => rdata,
		full	 => full_sig,
		empty	 => empty_sig,
		usedw	 => usedw_sig
	);
pulse_inst: component  pulse PORT MAP (
		 clk    =>fclk,
	         sin    =>swr,    -- если изменение от 0 в 1
		 pulse  =>wres);  -- выдаем pulse в 1 клок
pulse_inst2: component  pulse PORT MAP (
		 clk    =>fclk,
	         sin    =>srd,    -- если изменение от 0 в 1
		 pulse  =>rres);  -- выдаем pulse в 1 клок
		fifo_clk <= fifo_clkr or fifo_clkw;
process(fclk,wres)
begin
	  if   (wres = '1') then wstate <= "00";
	  elsif (rising_edge(fclk)) then
		case wstate is
		when "00" => wstate <= "01";
			     wrreq_sig <= '1';
		when "01" => wstate <= "10";
			     fifo_clkw <= '1';
		when "10" => wstate <= "11";
 			     fifo_clkw <= '0';
			     wrreq_sig <= '0';
		end case;
	  end if;
end process;
process(fclk,rres)
begin
	  if   (rres = '1') then rstate <= "00";
	  elsif (rising_edge(fclk)) then
		case rstate is
		when "00" => rstate <= "01";
			     rdreq_sig <= '1';
 		when "01" => rstate <= "10";
			     fifo_clkr <= '1';
		when "10" => rstate <= "11";
			     fifo_clkr <= '0';
			     rdreq_sig <= '0';
		end case;
	  end if;
end process;
END rw_fifo;