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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.std_logic_unsigned.all;
entity count_load is
port(
F56 : in std_logic;
foutr : out std_logic_vector (3 downto 0);
reset : in std_logic;
IZP : out std_logic
);
end count_load;
architecture a of count_load is
signal cntr : std_logic_vector (3 downto 0);
process (F56)
begin
if reset = '1' then
cntr <= (others => '0');
elsif (F56'event and F56 = '1') then
if cntr = "1110" then
cntr <= "0000";
else
cntr <= cntr + 1;
end if;
end if;
end process;
IZP <= cntr(3);
foutr <= cntr;
end a;
Все равно, также. Компилю в максе. Может он в принципе не понимает. Попробую в квартусе.
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