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architecture a of count_load is
signal cnt : std_logic_vector (20 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if cnt = 475416 then
cnt <= "001110100000100011000";
else
cnt <= cnt + 1;
end if;
end if;
end process;
f <= cnt(20);
end a;
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