Отправлено Doka 12 мая 2004 г. 23:25

Синтезирую следующий vhdl-код:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp_mixer is
Generic ( w_in: positive := 18;
w_dds: positive := 16;
w_16: positive := 16;
w_32: positive := 32 );
Port ( clk4x : in std_logic;
clk2x : in std_logic;
ce : in std_logic;
rst : in std_logic;
din_i : in std_logic_vector(w_in-1 downto 0);
din_q : in std_logic_vector(w_in-1 downto 0);
cos : in std_logic_vector(w_dds-1 downto 0);
sin : in std_logic_vector(w_dds-1 downto 0);
ch_mux : in std_logic;
-- out_ch : out std_logic;
-- valid : out std_logic;
-- dout_i : out std_logic_vector(32 downto 0);
dout : out std_logic_vector(w_dds+w_in-1 downto 0)); --34
end comp_mixer;

architecture arch_comp_mixer of comp_mixer is
signal op, clk : std_logic;
signal mx_i, mx_q, dds_i, dds_q : std_logic_vector(w_dds-1 downto 0); --16
signal i_int, q_int : std_logic_vector(w_in-1 downto 0); --18
signal ics, qcs : std_logic_vector(w_dds+w_in-2 downto 0); --33
signal mult_i, mult_q, dout_int : std_logic_vector(w_dds+w_in-1 downto 0); --34

begin
op <= clk2x;
clk <= clk4x;
mx_i <= cos when (clk2x='0') else sin;
mx_q <= cos when (clk2x='1') else sin;
mult_i <= signed(i_int) * signed(dds_i);
mult_q <= signed(q_int) * signed(dds_q);

dout_int <= (signed(ics(w_dds+w_in-2)&ics) + signed(qcs(w_dds+w_in-2)&qcs)) when (op='0')
else (signed(ics(w_dds+w_in-2)&ics) - signed(qcs(w_dds+w_in-2)&qcs)) when (op='1');

process(clk, rst, ce)
begin
if (ce = '1') then
if ( rst = '1') then
i_int <= (others=>'0');
q_int <= (others=>'0');
dds_i <= (others=>'0');
dds_q <= (others=>'0');
ics <= (others=>'0');
qcs <= (others=>'0');
dout <= (others=>'0');
elsif ( clk'event and clk ='1') then
i_int <= din_i;
q_int <= din_q;
dds_i <= mx_i;
dds_q <= mx_q;
ics <= mult_i(w_dds+w_in-2 downto 0);
qcs <= mult_q(w_dds+w_in-2 downto 0);
dout <= dout_int;
end if;
end if;
end process;
end arch_comp_mixer;

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Синтезатор - Леонардо 2004
кристалл: xc3s400, package fg456
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после Place&Route получаю следующий отчет:

Device utilization summary:

Number of External IOBs 106 out of 264 40%
Number of LOCed External IOBs 0 out of 106 0%

Number of Slices 387 out of 3600 10%
Number of MULT18X18s 2 out of 16 12%

Number of BUFGMUXs 1 out of 8 12%
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ДИКОСТЬ!!!! откуда столько заюзанных ячеек набегает?!?!?!

При использовании XST Place&Route-report выдает следующее:

Device utilization summary:

Number of External IOBs 106 out of 264 40%
Number of LOCed External IOBs 0 out of 106 0%

Number of Slices 69 out of 3600 1%
Number of MULT18X18s 2 out of 16 12%

Number of BUFGMUXs 1 out of 8 12%

притом сам 34-разрядный сумматор вычитатель при отдельном синтезе в Лео занимает законные 17 ячеек..

ВОПРОС: в чем прикол?