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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--=============================================================================
ENTITY position_latch IS
GENERIC (WIDTH : integer :=16);
PORT (
DATA : IN std_logic_vector (15 downto 0);
RST : IN std_logic;
CLK : IN std_logic;
OE : IN std_logic;
Q : OUT std_logic_vector(15 downto 0)
);
END position_latch ;
--=============================================================================
ARCHITECTURE behv OF position_latch IS
signal Qtmp : std_logic_vector(15 downto 0);
BEGIN
--=============================================================================
SS: PROCESS(Clk, rst)
BEGIN
if (RST = '0') then
Qtmp <= "0000000000000000";
elsif (Clk'event and Clk = '1') then
Qtmp <= DATA;
end if;
END PROCESS SS;
Q<=Qtmp
when OE ='1'
else "ZZZZZZZZZZZZZZZZ";
--=============================================================================
END behv;
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