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module mem_8i_32o(CLK_i,D8_i, WE_i,AI4_i,AO2_i,D32_o );
input CLK_i;
input [7:0]D8_i;
input WE_i;
input [3:0]AI4_i;
input [1:0]AO2_i;
output [31:0]D32_o;
reg [7:0]MemBlok_0[15:0];
reg [7:0]MemBlok_1[15:0];
reg [7:0]MemBlok_2[15:0];
reg [7:0]MemBlok_3[15:0];
always @(posedge CLK_i)
if(WE_i)
begin
MemBlok_0[AI4_i]=D8_i;
MemBlok_1[AI4_i]=D8_i;
MemBlok_2[AI4_i]=D8_i;
MemBlok_3[AI4_i]=D8_i;
end
wire[3:0]aout_0,aout_1,aout_2,aout_3;
assign aout_0[1:0]=0,aout_0[3:2]=AO2_i;
assign aout_1[1:0]=1,aout_1[3:2]=AO2_i;
assign aout_2[1:0]=2,aout_2[3:2]=AO2_i;
assign aout_3[1:0]=3,aout_3[3:2]=AO2_i;
assign D32_o[7:0] =MemBlok_0[aout_0];
assign D32_o[15:8] =MemBlok_1[aout_1];
assign D32_o[23:16]=MemBlok_2[aout_2];
assign D32_o[31:24]=MemBlok_3[aout_3];
endmodule
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