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ENTITY reg IS
GENERIC(
width_bus : positive := 8
);
PORT(
clk : IN std_logic;
din : IN std_logic_vector (width_bus - 1 DOWNTO 0);
reset : IN std_logic;
dout : OUT std_logic_vector (width_bus - 1 DOWNTO 0)
);
-- Declarations
END reg ;
ARCHITECTURE untitled OF reg IS
BEGIN
proc : process (clk, reset)
variable o_data : std_logic_vector(width_bus - 1 downto 0);
begin
if (reset = '1') then
o_data := (others => '0');
elsif clk'event and (clk = '1') then
o_data := din;
end if;
dout <= o_data;
end process proc;
END untitled;
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