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// testlz
`timescale 1 ns/100 ps
module testlz;
parameter w=12, n=6;
reg clk;
reg signed [w-1:0] d;
wire signed [w-1:0] q;
initial d=0;
initial begin clk = 0; #5 forever #5 clk = !clk; end
initial #100 $stop;
always @(posedge clk) begin
d=d+1;
end
lzx #(w,n) lz0(clk,d,q);
endmodule
// lzx
`timescale 1 ns/100 ps
module lzx(clk, d, q);
parameter w=12, n=6;
input clk;
input signed [w-1:0] d;
output signed [w-1:0] q;
reg [w-1:0] mas[n-1:0];
integer i;
assign q=mas[w-1];
always @ (posedge clk) begin
mas[0]<=d;
for (i = 1; i < n; i = i + 1) begin
mas[i] <= mas[i-1];
end
end
endmodule
//vsim presynth.testlz; view wave; add wave /testlz/lz0/*; run -all
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