Отправлено Сидоргек 27 февраля 2004 г. 13:06 В ответ на: Ну, не совсем ручками. Пришлось написать самопальный кодгенератор на С. А оптимизацию сгенерированного им кода на Верилоге доверил Синплифи. отправлено Сидоргек 27 февраля 2004 г. 13:03

// 57 активных коеффициентов
// Коеффициент интерполяции 4
// 15 элементов линии задержки

`timescale 1ps / 1ps

module filter_core (rst, clk, i_inp, q_inp, phase, iq, outp);
input rst;
wire rst;
input clk;
wire clk;
input [3:0] i_inp;
wire [3:0] i_inp;
input [3:0] q_inp;
wire [3:0] q_inp;
input [1:0] phase;
wire [1:0] phase;
input iq;
wire iq;
output [14:0] outp;
wire [14:0] outp;

wire dl_next;
assign dl_next = (phase == 3) && iq;

reg [3:0] dli [14:0];
reg [3:0] dlq [14:0];
integer dlcnt;
always @ (posedge clk or posedge rst) begin
if (rst) begin
for (dlcnt = 0; dlcnt < 15; dlcnt = dlcnt + 1) begin
dli[dlcnt] <= 7;
dlq[dlcnt] <= 7;
end
end
else begin
if (dl_next) begin
dli[0] <= i_inp;
dlq[0] <= q_inp;
for (dlcnt = 1; dlcnt < 15; dlcnt = dlcnt + 1) begin
dli[dlcnt] <= dlq[dlcnt-1];
dlq[dlcnt] <= dli[dlcnt-1];
end
end
else begin
for (dlcnt = 0; dlcnt < 15; dlcnt = dlcnt + 1) begin
dli[dlcnt] <= dlq[dlcnt];
dlq[dlcnt] <= dli[dlcnt];
end
end
end
end

function [4:0] fdlconv;
input [3:0] dl;
begin
fdlconv[4:1] = dl[3:0];
fdlconv[0] = 0;
end
endfunction

wire [14:0] fs0_0;
assign fs0_0 = -7395 - 7 * fdlconv(dli[0]) + 9 * fdlconv(dli[1]) ;
wire [14:0] fs0_1;
assign fs0_1 = - 11 * fdlconv(dli[2]) + 13 * fdlconv(dli[3]) - 15 * fdlconv(dli[4]) ;
wire [14:0] fs0_2;
assign fs0_2 = + 16 * fdlconv(dli[5]) - 17 * fdlconv(dli[6]) + 517 * fdlconv(dli[7]) ;
wire [14:0] fs0_3;
assign fs0_3 = - 17 * fdlconv(dli[8]) + 16 * fdlconv(dli[9]) - 15 * fdlconv(dli[10]) ;
wire [14:0] fs0_4;
assign fs0_4 = + 13 * fdlconv(dli[11]) - 11 * fdlconv(dli[12]) + 9 * fdlconv(dli[13]) ;
wire [14:0] fs0_5;
assign fs0_5 = - 7 * fdlconv(dli[14]) ;
wire [14:0] fs1_0;
assign fs1_0 = -7545 - 2 * fdlconv(dli[0]) - 1 * fdlconv(dli[1]) ;
wire [14:0] fs1_1;
assign fs1_1 = + 5 * fdlconv(dli[2]) - 11 * fdlconv(dli[3]) + 23 * fdlconv(dli[4]) ;
wire [14:0] fs1_2;
assign fs1_2 = - 48 * fdlconv(dli[5]) + 136 * fdlconv(dli[6]) + 462 * fdlconv(dli[7]) ;
wire [14:0] fs1_3;
assign fs1_3 = - 99 * fdlconv(dli[8]) + 55 * fdlconv(dli[9]) - 37 * fdlconv(dli[10]) ;
wire [14:0] fs1_4;
assign fs1_4 = + 26 * fdlconv(dli[11]) - 18 * fdlconv(dli[12]) + 12 * fdlconv(dli[13]) ;
wire [14:0] fs2_0;
assign fs2_0 = -7590 + 7 * fdlconv(dli[0]) - 12 * fdlconv(dli[1]) ;
wire [14:0] fs2_1;
assign fs2_1 = + 21 * fdlconv(dli[2]) - 33 * fdlconv(dli[3]) + 55 * fdlconv(dli[4]) ;
wire [14:0] fs2_2;
assign fs2_2 = - 101 * fdlconv(dli[5]) + 316 * fdlconv(dli[6]) + 316 * fdlconv(dli[7]) ;
wire [14:0] fs2_3;
assign fs2_3 = - 101 * fdlconv(dli[8]) + 55 * fdlconv(dli[9]) - 33 * fdlconv(dli[10]) ;
wire [14:0] fs2_4;
assign fs2_4 = + 21 * fdlconv(dli[11]) - 12 * fdlconv(dli[12]) + 7 * fdlconv(dli[13]) ;
wire [14:0] fs3_0;
assign fs3_0 = -7545 + 12 * fdlconv(dli[0]) - 18 * fdlconv(dli[1]) ;
wire [14:0] fs3_1;
assign fs3_1 = + 26 * fdlconv(dli[2]) - 37 * fdlconv(dli[3]) + 55 * fdlconv(dli[4]) ;
wire [14:0] fs3_2;
assign fs3_2 = - 99 * fdlconv(dli[5]) + 462 * fdlconv(dli[6]) + 136 * fdlconv(dli[7]) ;
wire [14:0] fs3_3;
assign fs3_3 = - 48 * fdlconv(dli[8]) + 23 * fdlconv(dli[9]) - 11 * fdlconv(dli[10]) ;
wire [14:0] fs3_4;
assign fs3_4 = + 5 * fdlconv(dli[11]) - 1 * fdlconv(dli[12]) - 2 * fdlconv(dli[13]) ;
wire [14:0] fs1_5;
assign fs1_5 = 0;
wire [14:0] fs2_5;
assign fs2_5 = 0;
wire [14:0] fs3_5;
assign fs3_5 = 0;

// Промежуточные регистры сумматора
reg [14:0] sum;
reg [14:0] sum0;
reg [14:0] sum1;
reg [14:0] sum2;
reg [14:0] sum3;
reg [14:0] sum4;
reg [14:0] sum5;
always @ (posedge clk or posedge rst) begin
if (rst) begin
sum0 <= 0;
sum1 <= 0;
sum2 <= 0;
sum3 <= 0;
sum4 <= 0;
sum5 <= 0;
sum <= 0;
end
else begin
case(phase)
0: begin
sum0 <= fs0_0;
sum1 <= fs0_1;
sum2 <= fs0_2;
sum3 <= fs0_3;
sum4 <= fs0_4;
sum5 <= fs0_5;
end
1: begin
sum0 <= fs1_0;
sum1 <= fs1_1;
sum2 <= fs1_2;
sum3 <= fs1_3;
sum4 <= fs1_4;
sum5 <= fs1_5;
end
2: begin
sum0 <= fs2_0;
sum1 <= fs2_1;
sum2 <= fs2_2;
sum3 <= fs2_3;
sum4 <= fs2_4;
sum5 <= fs2_5;
end
3: begin
sum0 <= fs3_0;
sum1 <= fs3_1;
sum2 <= fs3_2;
sum3 <= fs3_3;
sum4 <= fs3_4;
sum5 <= fs3_5;
end
default: begin
sum0 <= 15'bxxxxxxxxxxxxxxx;
sum1 <= 15'bxxxxxxxxxxxxxxx;
sum2 <= 15'bxxxxxxxxxxxxxxx;
sum3 <= 15'bxxxxxxxxxxxxxxx;
sum4 <= 15'bxxxxxxxxxxxxxxx;
sum5 <= 15'bxxxxxxxxxxxxxxx;
end
endcase

sum <= sum0 + sum1 + sum2 + sum3 + sum4 + sum5;
end
end

assign outp = sum;

endmodule