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Вот пример и встроеного хелпа
In the file simple.tdf shown below, the state machine Clock is driven by the input clk. The state machine's asynchronous Reset signal is driven by reset, which is active high. In this design file, the declaration of the ena input in the Subdesign Section and the Boolean equation ss.ena = ena in the Logic Section connect the Clock Enable signal.
SUBDESIGN simple
(
clk, reset, ena, d : INPUT;
q : OUTPUT;
)
VARIABLE
ss: MACHINE WITH STATES (s0, s1);
BEGIN
ss.clk = clk;
ss.reset = reset;
ss.ena = ena;
CASE ss IS
WHEN s0 =>
q = GND;
IF d THEN
ss = s1;
END IF;
WHEN s1 =>
q = VCC;
IF !d THEN
ss = s0;
END IF;
END CASE;
END;
Все вроде понятно.
Но если происходит RESET то в какое состояние
переходит state machine?
И как из него выйти?
Если первое обьявленное то почему не указано?
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