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architecture DELAY of DELAY is
type mem is array (0 to 15) of STD_LOGIC_VECTOR (data_range - 1 downto 0);
signal sm0 : STD_LOGIC_VECTOR(data_range - 1 downto 0);
signal reg : mem;
begin
process(clk)
begin
if clk = '1' and clk'event then
if ce = '1' then
reg <= d_in & reg(0 to 14);
end if;
end if;
end process;
process(clk,rst)
begin
if rst = '1' then
sm0 <= (others => '0');
elsif clk = '1' and clk'event then
if ce = '1' then
sm0 <= sm0 + reg(conv_integer(A));
end if;
end if;
end process;
d_out <= sm0;
Нет проблем. Для 16 разрядов:
Number of Slices: 16 out of 768 2%
Number of Slice Flip Flops: 16 out of 1,536 1%
Total Number 4 input LUTs: 32 out of 1,536 2%
Number used as LUTs: 16
Number used as Shift registers: 16
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