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 - mAVR

SM 11 2004 . 17:04
: Oru: (+) SM 11 urp| 2004 s. 15:31

pxtu| "Shift register support". Rp~yp 2-20.

"The size of a w ~ m ~ n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w ~ m ~ n shift register must be less than or equal to the maximum number of memory bits in the M4K block (4,608 bits). The total number of shift register outputs (number of taps n ~ width w) must be less than the maximum data width of the M4K RAM block (~36). To create larger shift registers, multiple memory blocks are cascaded together."

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