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на здоровье, больше не болей...
Вообще-то скачай полную версию Leonardo.
насчет Level ... 3 вот что в хелпе:
LeonardoSpectrum Modular Levels
The follow description compares and contrasts the three modular tool levels of LeonardoSpectrum. All three levels are powered by the same core synthesis and optimization engine which yields superior design results with a minimum of tool manipulation; and at the same time, allows you to control and guide the design transformation process.
The design methodology and control mechanisms become more detailed with each successive level: Level 1 produces the basic netlist, Level 2 adds more refined design control capabilities; and Level 3 contributes the ultimate in interactive, advanced features.
Level 1
Level 1 is an easy-to-use, single FPGA technology, synthesis tool that uses the LeonardoSpectrum hierarchical in-memory database. You simply select the input design and target technology and then click the Run Flow button. A high-quality netlist is quickly produced.
Level 1 includes the following clearly defined features:
Windows 98/2000/NT/XP node-locked platform
Single FPGA vendor
Certified FPGA flows
Global constraints (frequency, period, input to register, register to register, register to output, input to output)
Technology-independent specifications
Technology-specific operator generation
Architecture-specific optimization
Automatic or manual place and route invocation (P&RIntegrator) for Xilinx, Altera Max+PLUSII, Altera Quartus, and Lattice technologies.
Integrated source code editor (HDLInventor) including template insertion and error/warning cross highlighting
Single pass area and timing optimization
Batch Mode Operations (See the LeonardoSpectrum Reference Manual).
TCL Scripting
Easy upgrade path to Levels 2 and 3
Level 2
Level 2 is an easy-to-use FPGA synthesis and timing analysis tool for all FPGA technologies. You simply select you input design file(s) and FPGA or CPLD technology, optionally set global timing constraints (like the clock frequency) and then click the Run Flow button. A high-quality netlist is quickly produced. Optionally, you may also choose to automatically run Integrated Place and Route at the end of the flow. In contrast to Level 1, Level 2 is for all FPGA technologies. Level 2 contributes to the extensive features list of Level 1 with the following:
Platform independent on Windows 98/2000/NT/XP or UNIX
All FPGA technologies
Certified FPGA flows: Generated netlists and directives successfully pass through the back-end tools.
Hierarchy Preservation
Advanced Constraints
Advanced Optimization Switches
Retarget Output Netlist
Accurate architecture specific timing analysis
Optimizes designs for area and speed, and accepts designs as either HDL structural netlists or as RTL (register transfer level)
Vendor specific netlists are produced together with design reports that provide estimates of design performance
Easy upgrade path to Level 3
Level 3
Level 3 is an easy-to-use, versatile and interactive logic synthesis, optimization, and analysis tool. Level 3 allows you to use technology-independent design methods for FPGA and CPLD devices, and in contrast to Levels 1 and 2, Level 3 optionally supports advanced algorithms to target ASIC technologies. You can perform bottom-up design assembly with a technology-mapped netlist. Hierarchy can be preserved, flattened, merged and dissolved. Plus, complex scripts can be written and run through an interactive batch mode operation. The design effort can be accomplished either by an individual engineer or by a team of engineers.
Level 3 utilizes the most powerful state-of-the-art optimization technology to guarantee high-quality results for any FPGA or ASIC technology. Level 3 adds to the long list of Level 2 features with the following:
Optional ASIC specific module generation, optimization algorithms, design rule resolving, and technology mapping
Two-way retarget path exists between FPGA synthesis and optional ASIC synthesis
Mix HDL Design entry - for example, Verilog, VHDL, EDIF
Interactive Command Line Shell that gives you full access to the in-memory design database
Design Browser with Commands
Advanced TCL Scripting
Incremental optimization which allows bottom up, top down, and team design
RTL and gate-level post-synthesis verification
You can run Level 3 from the GUI interactive command line shell or from TCL script files. Batch mode is also available for Level 3. LeonardoSpectrum is designed to give you easy access to the Model Technology ModelSim simulator.
Level 3 provides a top-down verification flow through VHDL or Verilog with an SDF timing file.
Additional Standard Features
The following additional standard features allow you to complete the entire synthesis task within LeonardoSpectrum. These features are:
HDLInventor
Design Browser (Level 3)
Tcl Script Sourcing
P&RIntegrator
E-mail: 
info@telesys.ru
