TITLE "SYSTEM CONTROLLER";
INCLUDE "LPM_LATCH";
SUBDESIGN SYS_CONT
(
AD[15..0] : BIDIR;
ALE : INPUT;
BHE : INPUT;
DEN : INPUT;
DTR : INPUT;
RD : INPUT;
WR : INPUT;
GCS[7..0] : INPUT;
D[15..0] : BIDIR;
A[15..0] : OUTPUT;
/WLB : OUTPUT;
/WHB : OUTPUT;
/CS[7..0] : OUTPUT;
)
VARIABLE
Z_AD[15..0] : TRI;
Z_D[15..0] : TRI;
ALATCH : LPM_LATCH WITH(LPM_WIDTH = 16);
ADDR0 : NODE;
/RW : LCELL;
BEGIN
DEFAULTS
/WLB = VCC;
/WHB = VCC;
/CS[7..0] = VCC;
END DEFAULTS;
Z_AD[].IN = D[]; Z_AD[].OE = !(ALE # DEN # DTR);
AD[] = Z_AD[].OUT;
Z_D[].IN = AD[]; Z_D[].OE = !DEN & DTR;
D[] = Z_D[].OUT;
ALATCH.(DATA[],GATE) = (AD[],ALE);
A[] = ALATCH.Q[]; ADDR0 = ALATCH.Q0;
/WLB = !ADDR0 NAND !WR;
/WHB = !BHE NAND !WR;
/RW.IN = RD & /WLB & /WHB;
/CS[] = !GCS[] NAND !/RW;
END;