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Ia kogda poluchil s proizvodstva plati s etimi DSP, to bili teje problemi.
1. Esli DSP rabotaet v PLL mode, to interval reset doljen bit^ minimum 250 uS. V moment pod'ema reseta (zadnii front) vse ustanovki na XBUS doljni bit^ stabil^ni.
2. DSP etot ochen^ moschnii. Tok perexodnogo processa v moment starta v neskol^ko raz previshaet sredniu normu potreblemia. Esli PS ne vitiagivaet to chto trebuet DSP to eto privodit k sboiu v PLL, v ustanovkax registrov i pr.
Udachi i s Novim Godom
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