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Для начала вот исходник, делает пилу на цапе, используем dma chaining, но пила получается немного гуляющая по времени - думается мне, что из-за ихнего кита, у меня вроде все правильно написано, другие исходники кинуть??: volatile int k=0; volatile long ReadLeft, ReadRight, WriteLeft, WriteRight; #pragma align 4 #pragma align 4 #pragma align 4 void SetTCB0(long DI_S,long DX_S,long DY_S,long DP_S,long DI_D,long DX_D,long DY_D,long DP_D) } void Init_DSP(void) __builtin_sysreg_write(__SYSCON, SYSCON_MP_WID64 | __builtin_sysreg_write(__SDRCON, SDRCON_INIT | temp = __builtin_sysreg_read(__SQCTL); interruptf(SIGDMA0, audio_int); WL_S.DP=(((long)(&WR_S)>>2)&0x7fff)|TCB_INTMEM | TCB_DMAR |TCB_NORMAL | TCB_CHAIN | TCB_DMA0SOURCE | TCB_CHAINPTRM1; SetTCB0(WL_S.DI,WL_S.DX,WL_S.DY,WL_S.DP, WL_D.DI,WL_D.DX,WL_D.DY,WL_D.DP ); //Wkluchaem CODEC... void main(void) }
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#include "TS101Def.h"
#include "TSEZKitDef.h"
#include
#include
#include
#include
#include
typedef struct
{
long DI,DX,DY,DP;} TCB;
volatile long Sin_Buf[96];
#pragma align 4
TCB RL_S=
{CODEC, 0x00010000,0,0
};
#pragma align 4
TCB RL_D=
{ (long)&ReadLeft, 0x00010000,0,0
};
TCB RR_S=
{CODEC, 0x00010000,0,0
};
#pragma align 4
TCB RR_D=
{(long)&ReadRight, 0x00010000,0,0
};
TCB WL_S=
{(long) &WriteLeft, 0x00010000,0,0
};
#pragma align 4
TCB WL_D=
{CODEC, 0x00010000,0,0
};
TCB WR_S=
{(long) &WriteLeft,0x00010000,0,0};
#pragma align 4
TCB WR_D=
{CODEC,0x00010000,0,0
};
void audio_int( ){
k+=1;
if (k==96) k=0;
WriteLeft=Sin_Buf[k];
};
{
volatile __builtin_quad TCB_clear, TCB_set;
TCB_clear=__builtin_compose_128((long long)TCB_DISABLE<<32,0);
__builtin_sysreg_write4(__DCS0,TCB_clear);
__builtin_sysreg_write4(__DCD0,TCB_clear);
TCB_set=__builtin_compose_128( ((long long)DX_S<<32)|DI_S, ((long long) DP_S<<32)|DY_S);
__builtin_sysreg_write4(__DCS0,TCB_set);
TCB_set=__builtin_compose_128( ((long long)DX_D<<32)|DI_D, ((long long) DP_D<<32)|DY_D);
__builtin_sysreg_write4(__DCD0,TCB_set);
{
volatile int temp;
SYSCON_MEM_WID64 |
SYSCON_MSH_SLOW |
SYSCON_MSH_WT3 |
SYSCON_MSH_IDLE |
SYSCON_MS1_SLOW |
SYSCON_MS1_WT3 |
SYSCON_MS1_IDLE |
SYSCON_MS0_SLOW |
SYSCON_MS0_WT3 |
SYSCON_MS0_IDLE);
SDRCON_RAS2PC4 |
SDRCON_PC2RAS3 |
SDRCON_REF600 |
SDRCON_PG1K |
SDRCON_CLAT2 |
SDRCON_ENBL);
temp = __builtin_sysreg_read(__IMASKL);
temp = temp | INT_DMA0;
__builtin_sysreg_write(__IMASKL, temp);
temp = __builtin_sysreg_read(__IMASKH);
temp = temp | INT_GIE;
__builtin_sysreg_write(__IMASKH, temp);
temp = temp | SQCTL_FLAG3_EN;
temp = temp & (~SER_ENBL);
__builtin_sysreg_write(__SQCTL, temp);
WL_D.DP=(((long)(&WR_D)>>2)&0x7fff)|TCB_EXTMEM | TCB_DMAR |TCB_NORMAL | TCB_CHAIN | TCB_DMA0DEST | TCB_CHAINPTRM1;
WR_S.DP=(((long)(&WL_S)>>2)&0x7fff)|TCB_INTMEM | TCB_NORMAL | TCB_CHAIN | TCB_INT | TCB_DMA0SOURCE | TCB_CHAINPTRM1;
WR_D.DP=(((long)(&WL_D)>>2)&0x7fff)|TCB_EXTMEM | TCB_NORMAL | TCB_CHAIN | TCB_INT | TCB_DMA0DEST | TCB_CHAINPTRM1;
temp = __builtin_sysreg_read(__SQCTL);
temp = temp | SER_ENBL;
__builtin_sysreg_write(__SQCTL, temp);
}
{
for(k=0;k<96;k++)
{
//Sin_Buf[k]=(long) (8000000*(sin(k*2*3.141596/96)));
Sin_Buf[k]=(long) ((-1)*8388607+2*8388607*k/96);
}
k=0;
Init_DSP();
while(1){
//temp=1;
};
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