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Возникает куча проблем. Флаг Owner'а в DMA, какие-то "пустые" прерывания при передаче. Вообщем-то у меня работает, но после несколькольких килобайтный посылок передача умирает полностью -
DMA SPORT'а отказывается работать. Как это убрать - не знаю.
Наверно придеться какой-нибудь таймер добавлять.
Текст программы (по SPORT'у) ниже. Есть желание - разирайся.
Меня пока загрузили другим, так что существенной помощи от меня не стоит требовать :)
/********* SPORT ****************/
#ifdef SPORT2
#define SPx_Controller_Page SPORT2_Controller_Page
#define SPx_TCR SP2_TCR
#define SPx_RCR SP2_RCR
#define SPx_TSCKDIV SP2_TSCKDIV
#define SPx_RSCKDIV SP2_RSCKDIV
#define SPxDT_CFG SP2DT_CFG //Transmit DMA Configuration
#define SPxDT_CP SP2DT_CP //Transmit DMA Chain Pointer
#define SPxDT_CPR SP2DT_CPR //Transmit DMA Chain Pointer Ready
#define SPxDR_CFG SP2DR_CFG //Receive DMA Configuration
#define SPxDR_CP SP2DR_CP //Receive DMA Chain Pointer
#define SPxDR_CPR SP2DR_CPR //Receive DMA Chain Pointer Ready
#define SPxDR_IRQ SP2DR_IRQ //Receive DMA Interrupt Register
#define SPxDT_IRQ SP2DR_IRQ //Transmit DMA Interrupt Register
#define SPxDR_SRP SP2DR_SRP // SPORT RX DMA Internal Memory Page
#define SPxDR_SRA SP2DR_SRA //SPORT RX DMA Internal Memory Address
#define SPxDR_CNT SP2DR_CNT //SPORT RX DMA Internal Memory Count
#endif
#ifdef SPORT1
#define SPx_Controller_Page SPORT1_Controller_Page
#define SPx_TCR SP1_TCR
#define SPx_RCR SP1_RCR
#define SPx_TSCKDIV SP1_TSCKDIV
#define SPx_RSCKDIV SP1_RSCKDIV
#define SPxDT_CFG SP1DT_CFG //Transmit DMA Configuration
#define SPxDT_CP SP1DT_CP //Transmit DMA Chain Pointer
#define SPxDT_CPR SP1DT_CPR //Transmit DMA Chain Pointer Ready
#define SPxDR_CFG SP1DR_CFG //Receive DMA Configuration
#define SPxDR_CP SP1DR_CP //Receive DMA Chain Pointer
#define SPxDR_CPR SP1DR_CPR //Receive DMA Chain Pointer Ready
#define SPxDR_IRQ SP1DR_IRQ //Receive DMA Interrupt Register
#define SPxDT_IRQ SP1DR_IRQ //Transmit DMA Interrupt Register
#define SPxDR_SRP SP1DR_SRP // SPORT RX DMA Internal Memory Page
#define SPxDR_SRA SP1DR_SRA //SPORT RX DMA Internal Memory Address
#define SPxDR_CNT SP1DR_CNT //SPORT RX DMA Internal Memory Count
#endif
#define cInitTCR (SportWordLength+ SportEnable+ InternalClock+InternalFrame+TFSRequired+ClockFallingEdge)
#define cInitRCR (SportWordLength+InternalClock+ SportEnable +LateFrameSync )
#define SportBit 0x01C0;
///-----------SPORT --------
.var SP1TranBuff[13];
.var SP1RecBuff[9];
.var SP1CurrTranByte; //counter for transmiting byte of SPORT buffer
.var SP1RxDes[5]=
0x8007, // Enable DMA, interrupt on completion, memory write,software control
PAGE(SP1RecBuff),
SP1RecBuff,
LENGTH(SP1RecBuff),
SP1RxDes+1;
.var SP1TxDes[5]=
0x0105, // Disable DMA, interrupt on completion, software control,int-t on error?
PAGE(SP1TranBuff),
SP1TranBuff,
LENGTH(SP1TranBuff),
SP1TxDes+1;
//-----------------
.SECTION /pm program;
Initialize_SPORT1:
iopg=SPx_Controller_Page;
ax0 = dm(_VarLoad->SPORT_div);ax1=0xFF;
ar=ax0 and ax1;io(SPx_TSCKDIV)=ar;
sr=lshift ax0 by -8(lo);io(SPx_RSCKDIV)=sr0;
ar=0; io(SPx_TCR)=ar; //set tcr
ar=cInitRCR; io(SPx_RCR)=ar;
ar=0x8007;dm(SP1RxDes)=ar; //set descriptor
ar=SP1RxDes;io(SPxDR_CP)=ar; //load descriptor
ar=0x01;io(SPxDR_CPR) = ar; // DMA Descriptor Ready
ar=0x01;io(SPxDR_CFG) = ar; //start DMA Recieve
RTS;
SPORT1_start_transmit:
ax0=0;dm(SP1CurrTranByte)=ax0;
ax0=dm(_EventsFlag);ar=setbit evSPORT_Tran of ax0;
dm(_EventsFlag)=ar;//set transmiting flag
iopg=SPx_Controller_Page;
ax0=0;io(SPx_RCR)=ax0; //Stop recieve IrDA!
ar=0x0080;io(SPxDT_CFG)=ar; //clear DMA transmit
ar=cInitTCR;io(SPx_TCR)=ar; //set tcr
RTS;
/******** SPORT receive interrupt ***********/
SPORT_receive_inter:
ENA SR;
AY1=iopg;
iopg=SPx_Controller_Page;
do_while_not_clear1:
ax0=dm(SP1RxDes);af=ax0 and 0x8000;
if ne jump do_while_not_clear1;
ar=0x0000; io(SPx_RCR)=ar; //Disable Rx
ar=0x0082; io(SPxDR_CFG)=ar; //clear DMA
//Reading received byte
i6=SP1RecBuff+1;m6=1;l6=0;DMPG2=page(SP1RecBuff);
ax0=0xFF00;cntr=8;
DO SP_ReadReceivedByte_loop until CE;
sr=lshift ax0 by -1(lo);ax0=sr0;
ar=dm(i6+=m6);
sr=lshift ar by -1(lo);
ar=ar and sr0;
if eq jump SP_ReadReceivedByte_loop;
ar=clrbit 7 of ax0; ax0=ar;
SP_ReadReceivedByte_loop:
nop;
// working with received byte
ax1=dm(_SPORT1_Buf->RecCnt);
ay0=0;ar=ax1 or ay0;
if ne jump SP_add_to_buffer;
ay0=First_char_rec;ar=ax0 xor ay0;
if ne jump SP_ReadRec_exit;
SP_add_to_buffer:
i6=_SPORT1_Buf->RecBuf;m6=ax1;dm(i6+m6)=ax0; //store byte
ar=ax1+1;
//af=ar-1; if eq ar=ar+1; // omit net number
dm(_SPORT1_Buf->RecCnt)=ar;
ax1=dm(_EventsFlag); ar=setbit evSPORT_Rec of ax1; //set flag
dm(_EventsFlag)=ar;
SP_ReadRec_exit:
ar=0x8007;dm(SP1RxDes)=ar; //set descriptor
ar=SP1RxDes;io(SPxDR_CP)=ar; //load descriptor
ar=0x01;io(SPxDR_CPR) = ar; // DMA Descriptor Ready
ar=0x01;io(SPxDR_CFG) = ar; //start DMA Recieve
ar=cInitRCR; io(SPx_RCR)=ar; //Enable Rx
ar=3;io(SPxDR_IRQ)=ar; /* Clear RX Interrupts */
iopg=AY1;
dis SR;
rti;
/******** End of SPORT receive interrupt ***********/
/******** SPORT Transmit interrupt ***********/
SPORT_transmit_inter:
ENA SR;
ay1=IOPG;
IOPG=SPx_Controller_Page;
do_while_not_clear:
ax0=dm(SP1TxDes);af=ax0 and 0x8000;
if ne jump SPORT_transmit_inter_exit;//do_while_not_clear;
/*
//test only!
IOPG = General_Purpose_IO;
ar=0x10; io(FLAGS)=ar; //pf4 - high
IOPG=SPx_Controller_Page;
//test only!
*/
ax1=dm(SP1CurrTranByte); ax0=dm(_SPORT1_Buf->TranCnt);
ar=ax0-ax1;
if gt jump SP_Start_Transmit;
ax0=0x0; ar=ax1 - ax0;
if le jump SP_stop_transmit;
ax0=dm(_EventsFlag); ar=CLRBIT evSPORT_Tran of ax0; //clear transmit flag
ar=setbit evSPORT_StopTran of ar; //set SPORT "stop transmit" flag;
dm(_EventsFlag)=ar;
ax0=0;dm(_SPORT1_Buf->TranCnt)=ax0;//clear Tran counter
dm(SP1TranBuff+0)=ax0; //clear SP1TranBuff
dm(SP1TranBuff+1)=ax0;dm(SP1TranBuff+2)=ax0;dm(SP1TranBuff+3)=ax0;
dm(SP1TranBuff+4)=ax0;dm(SP1TranBuff+5)=ax0;dm(SP1TranBuff+6)=ax0;
dm(SP1TranBuff+7)=ax0;dm(SP1TranBuff+8)=ax0;
dm(SP1CurrTranByte)=ax0; //clear Current byte counter;
jump SPORT_transmit_buf; //send empty buffer
SP_stop_transmit:
ax0=0;
io(SPx_TCR)=ax0; io(SPx_TCR)=ax0; //stop Sport (write twice!)
dm(SP1TxDes)=ax0; //clear descriptor header
io(SPxDT_CFG) = ax0; //stop DMA Transmit
///????????
dm(SP1CurrTranByte)=ax0; //clear Current byte counter;
dm(_SPORT1_Buf->TranCnt)=ax0;//clear Tran counter
ax0=dm(_EventsFlag); ar=CLRBIT evSPORT_Tran of ax0; //clear transmit flag
ar=setbit evSPORT_StopTran of ar; //set SPORT "stop transmit" flag;
dm(_EventsFlag)=ar;
ax0=cInitRCR;io(SPx_RCR)=ax0; //Start recieve IrDA!
jump SPORT_transmit_inter_exit;
SP_Start_Transmit:
ax0=dm(_SPORT1_Buf->TranStartAdr);ar=ax0+ax1; //address for transmiting byte
i0=ar;m0=1;l0=0;ar=ax1+1;dm(SP1CurrTranByte)=ar;
ax0=dm(i0 += m0);
ar=SportBit;dm(SP1TranBuff+0)=ar;
af=TSTBIT 0x00 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+1)=ar;
ar=SportBit;af=TSTBIT 0x01 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+2)=ar;
ar=SportBit;af=TSTBIT 0x02 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+3)=ar;
ar=SportBit;af=TSTBIT 0x03 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+4)=ar;
ar=SportBit;af=TSTBIT 0x04 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+5)=ar;
ar=SportBit;af=TSTBIT 0x05 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+6)=ar;
ar=SportBit;af=TSTBIT 0x06 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+7)=ar;
ar=SportBit;af=TSTBIT 0x07 OF ax0;if ne ar= PASS 0; dm(SP1TranBuff+8)=ar;
SPORT_transmit_buf:
ar=0x8005;dm(SP1TxDes)=ar; //set descriptor
ar=SP1TxDes;io(SPxDT_CP)=ar; //load descriptor
ar=0x01;io(SPxDT_CPR) = ar; // DMA Descriptor Ready
ar=0x01;io(SPxDT_CFG) = ar; //start DMA Transmit
SPORT_transmit_inter_exit:
ax0=0x0003;io(SPxDT_IRQ)=ax0; //Clear Interrupt
//test only!
ax0=dm(_EventsFlag);
IOPG = General_Purpose_IO;
ar=tstbit evSPORT_Tran of ax0 ;
if eq jump set_0_pf4;
ar=0x10; io(FLAGS)=ar; //pf4 - high
// ar=0x00;dm(tmp)=ar;
jump set_1_pf4;
set_0_pf4:
ar=0x10; io(FLAGC)=ar; //pf4 - low
// ar=0x01;dm(tmp)=ar;
set_1_pf4:
//test only!
IOPG=ay1;
DIS SR;
rti;
/******** End of SPORT Transmit interrupt ***********/
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