С первым вроде ясно вот что прочитал, еле нашел :) The HAS input is not gated by HCS, therefore allowing time for the host to perform the subsequent access. The HAS signal may be brought high after internal HSTRB goes low, indicating that the data access is about to occur. HAS is not required to be driven high at any time during the cycle, but eventually must transition high before the host uses it for another access with different values for HCNTL [1:0], HR/W, and HBIL.