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3.11.2 даташита:
NOTE: The enable registers PGPIOENn cannot override the External Bus Selection Register (XBSR) setting.
таблица 3-6 даташита (регистр XBSR):
Parllel/Host Port Mux Mode bit. Determines the mode of the Parallel
Port Mux and the Host Port Mux.
• Parallel/Host Port Mux Mode = 0:
The Parallel Port Mux is configured to support PGPIO. In this
mode, the HPI and EMIF cannot be used.
The Host Port Mux is configured to support PGPIO. In this mode, the Host Port Mux pins will be routed to PGPIO.
• Parallel/Host Port Mux Mode = 1:
The Parallel Port Mux is configured to support the 32-bit EMIF. In
this mode, the EMIF is enabled and its 20 address, 32 data, and
16 control signals are routed to their corresponding pins on the
Parallel Port Mux.
The Host Port Mux is configured to support the HPI in 8-bit
(multiplexed) mode. In this mode, the HPI is enabled and its eight
data/address and two control signals are routed to their
corresponding pins on the Host Port Mux.
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