Îòïðàâëåíî off 28 èþíÿ 2004 ã. 07:28

1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0

1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
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Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0
1
As today’s designs increase in complexity, the ability to find and fix design problems through hardware
decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem
when looking at a chip. The solution to finding and fixing these problems is through software simulation.
Software simulation emulates real time operation of the internal logic as well as the external pins. By
probing different locations within the chip, simulation allows designers to trace problems back to the
source.
The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA
devices, the back-end compile times may be significantly longer than the synthesis compiles through
Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick
compile times thereby allowing designers to accurately debug functional design problems in a timely
manner.
This application note describes how to successfully integrate simulation into your design methodology.
This integration not only involves the simulation process but additionally uses test benches to run the
different types of simulations.
Topics to be covered:
? Simulation Flow
? Simulation Features
? HDL Testbenches
? Example 1: Functional Simulation (ModelSim)
? Example 2: Compiling the Mapped Netlist (Synplify)
? Example 3: Mapped-Functional Simulation (ModelSim)
? Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
? Example 5: Gate-Level Simulation With Timing (ModelSim)
Synthesis Guide for ModelSim rev 1.0
2
Section 2. The Design Flow
Designers have traditionally simulated the source code to check for syntax and functional problems. With
the HDL editor in Synplify designers may easily enter and simulate the mapped-functional netlist. The
functional simulation of the source code allows designers to check the general functionality without the full
design flow.
After synthesis, Synplify generates mapped functional simulation that uses unit delays. This mapped netlist
adds architecture specific structures to the functional simulation. With Synplify’s linear compile times,
even the largest Xilinx devices may be compiled in minutes. Designers can iterate more quickly through
their design cycle using the mapped, functional simulation generated from Synplify without running into
the longer Alliance place and route times.
The Alliance tools will additionally generate a VHDL or Verilog netlist with the routing delays annotated
into a Standard Delay Format (SDF) file. The simulation netlist settings may be set in the Alliance tools in
the IMPLEMENTATION OPTIONS window under the INTERFACE tab.
Simulation Features
As a leader in FPGA synthesis solutions, Synplify offers an efficient simulation flow for ModelSim.
Coupled with other debugging features and fast compile times, designers can quickly debug problems
within Synplify and ModelSim, minimizing the iterations through the Alliance tools.
Because a good simulation models true device behavior, functionally simulating the source code may not
be enough. If the simulation does not accurately represent device operation, a bad simulation may cause
designers to debug non-existent problems seen only during simulation or to miss critical board problems
during simulation. Because VHDL and Verilog were both originally created as a simulation language,
functional simulation of the source code will simulate following a set of guidelines for simulation and will
not be able to model true device behavior.
Gate Level
Simulation
synplify.vhd
ModelSim Synplify
HDL Design Entry
Synthesis
SIMPRIM
Library
Place & Route
Mapped-Functional
Simulation
RTL-Functional
Simulation
Figure 1: Design Flow
Alliance
Synthesis Guide for ModelSim rev 1.0
3
Only after using Synplify for synthesis will the device characteristics be incorporated into a mappedfunctional
simulation model that includes device characteristics. Due to the mapping, architecture specific
details will be mapped making the simulation accurately model true device behavior functionally.
Designers should simulate at the mapped-functional level to bypass longer compile times associated with
placing and routing the FPGA device through the Alliance tools. Synplify’s fast compile times allow
designers to run multiple compiles to isolate and debug problems before having to go through the full backend
design flow. When the design is functionally correct, the designer takes the design through the Alliance
tools to place and route the Xilinx device.
To make the simulation accurately model Xilinx devices, Synplify creates a mapped simulation netlist for
both VHDL and Verilog. These mapped simulation netlists use unit delays to model propagation delays.
Both VHDL and Verilog are structured down to the base cells, e.g. look-up-tables and carry chains.
To enhance simulations, both Synplify and ModelSim support VHDL ’93. Concerning library requirements
for simulation, only a small three-component VHDL library from Synplicity will be required
(/lib/vhdl_sim/synplify.vhd). The remainder of the VHDL is self-contained within the
simulation file. Synplify’s Verilog netlist is fully self-contained and does not require any other design files
to be compiled into ModelSim.
About Testbenches
A testbench is a separate set of VHDL or Verilog code that connects up to the inputs and outputs of a
design. Since the inputs and outputs of the design stay constant throughout the Synthesis and Place &
Route process, the testbench can usually be used at each stage to verify the functionality of the design. The
Testbench has two main purposes:
First, a testbench provides the stimulus and response information (clocks, reset, input data, etc.) that the
design will encounter when implemented in a FPGA device. Secondly, the testbench contains regression
checking constructs which allow key functionality to be tested throughout the FPGA HDL simulation flow
(whether a counter design is counting; whether a floating point unit has calculated the correct value; etc.).
Synthesis Guide for ModelSim rev 1.0
4
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component GUESSER
port (
DATA, CLK, RST : in std_logic;
GUESS : out std_logic);
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: GUESSER port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT: GUESSER
use entity work.GUESSER(behave);
END FOR;
END FOR;
end CFG_TB_GUESSER;
Figure 2: tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
5
Section 3. The Design Example
The design file can be found in the Synplify examples directory
\examples\vhdl\statmchs\statmch2.vhd. Create a working directory for this tutorial and copy the
design file.
For ModelSim, both the menu commands as well as the command lines “VSIM>” have been shown.
Example 1: Functional Simulation (ModelSim)
Prior to synthesizing and place & routing with the Xilinx tools, you will first compile and simulate the
"LAB" RTL design with Model Technology's ModelSim simulator.
1) Open ModelSim
2) Change directories to the working directory :
Select FILE=>DIRECTORY menu.
VSIM> cd
3) Create a WORK directory: Select LIBRARY=>NEW and enter in WORK
VSIM>vlib work
4) Open up VHDL Compiler menu: Click on the VCOM button.
5) Switch to VHDL’93: Click on the OPTIONS button and check “Use 1076-1993 language standard”
and ACCEPT.
Figure 3: Setting Compiler Options
6) Compile the VHDL design file and testbench:
a) Select STATMCH2
b) Click COMPILE
c) Select TSTATE_MCH2.VHD
d) Click COMPILE
e) Click on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
Synthesis Guide for ModelSim rev 1.0
6
7) Start simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Open the simulator windows: Select VIEW=>ALL
VSIM> view *
9) Clean up windows by tiling: Select Window=>Tile Horizontally
10) Add signals to waveform:
Select SIGNALS=>ADD TO WAVEFORM=>SIGNALS IN DESIGN
VSIM> wave *
VSIM> wave /dut/state
11) Run for 2000 ns
VSIM> run 2000
Note: See appendix A for a brief description of the ModelSim debugging
windows
Figure 4: ModelSim Simulation
Example 2: Compiling the Mapped Netlist (Synplify)
1) Open Synplify
2) Create a new project file and save to working directory:
a) Select FILE=>NEW “Project”
b) Select FILE=>SAVE AS
Synthesis Guide for ModelSim rev 1.0
7
3) Enable the VHDL or Verilog mapped netlists from the menus:
OPTIONS=>WRITE MAPPED VHDL/VERILOG NETLIST
Figure 5: Mapping To VHDL/Verilog in Synplify
Note: Synplify will create a vhdl (.vhm) or verilog (.vm) netlist in the
working directory.
4) Add the design files to be compiled:
Note: Add the designs in the reverse order of hierarchy with the top level design file added last to the
bottom of the list
Click on ADD (Source Files) “statmch2.vhd” to the compiler window
5) Start Compiling: Click on the Run button
Example 3: Mapped-Functional Simulation (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE FIRST TIME)
Pre-Compile Synplicity Synplify library:
a) Choose a directory to keep compiled libraries: /SYNPLIFY
b) Change to directory
c) Create a SYNPLIFY library: LIBRARY=>NEW and type SYNPLIFY
d) Open VHDL Compiler window: Click VCOM button
e) Change to /lib/vhdl_src directory
f) Change TARGET LIBRARY to SYNPLIFY
g) Compile synplify.vhd
j) Change TARGET LIBRARY back to WORK
Synthesis Guide for ModelSim rev 1.0
8
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: synplify
Directory: /synplify
l) Click OK in both windows
Figure 6: Compiling Synplify Library
3) Change directories to the working directory :
Open the FILE=>DIRECTORY menu
VSIM> cd
4) Create WORK library:
b) Select LIBRARY=>NEW and type WORK
VSIM>vlib work
5) Switch to VHDL’93 (use –93 option when using vcom in command line):
a) Click on VCOM button
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL files:
a) Show all the files: In SELECT FILES OF TYPE select ALL FILES
b) Select statmch2.vhm
c) Click on COMPILE
d) Select TSTATE_MCH2.VHD
e) Click on COMPILE
f) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM> vcom –93 statmch2.vhd
VSIM> vcom –93 tstate_mch2.vhd
7) Start Simulation: Click on VSIM and select the configuration cfg_tb_guesser.
VSIM> vsim cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
Synthesis Guide for ModelSim rev 1.0
9
VSIM> wave /dut/state
VSIM> run 2000
9) Setup display: Select Window=>Tile Horizontally
Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance)
1) Open Alliance
2) Create a new project: Select File=>New Project
Input Design: /statmch2.xnf
Work Directory:
Comment:
3) Enable Timing Simulation to create gate level netlist for HDL Simulation:
a) Select DESIGN=>IMPLEMENT
b) Click on OPTIONS
c) Check PRODUCE TIMING SIMULATION DATA (Optional Targets)
d) Keep DESIGN=>IMPLEMENT=>OPTIONS menu open
Figure 7: Setting Simulation Settings
4) Select the simulation format in DESIGN=>IMPLEMENT=>OPTIONS menu:
a) Click on EDIT TEMPLATE (Implementation)
b) Select INTERFACE tab
c) Select netlist preference (VHDL/Verilog)
d) Click OK to close EDIT TEMPLATE menu
e) Click OK to close OPTIONS menu
f) Keep IMPLEMENT menu open
5) Start compiling: Click on RUN
Alliance will start compiling STATMCH2.XNF and generate the gate-level simulation netlist files
automatically in the directory /xproj/ver1/rev1
Synthesis Guide for ModelSim rev 1.0
10
TIME_SIM.VHD: VHDL Netlist
TIME_SIM.SDF: Annotated Timing Delays
6) Close Flow Engine and Alliance Tools
Example 5: Gate-Level Simulation With Timing (ModelSim)
1) Open ModelSim
2) (MAPPING LIBRARY ONLY NEEDS TO BE DONE ONCE)
Pre-Compile Xilinx SIMPRIMS library:
a) Choose a directory to keep compiled libraries: /XILINX
b) Change to directory
c) Create a XILINX library: LIBRARY=>NEW and type XILINX
d) Open VHDL Compiler window: Click VCOM button
e) Change to /vhdl/src/simprims directory
f) Change TARGET LIBRARY to XILINX
g) Compile simprim_Vpackage.vhd
h) Compile simprim_VITAL.vhd
i) Compile simprim_Vcomponents
j) Change TARGET LIBRARY back to WORK
k) Map Compiled SIMPRIM library to directory:
Select LIBRARY=>MAPPING=>NEW
Library: Xilinx
Directory: /XILINX
l) Click OK in both windows
3) Change directories to the working directory /xproj/ver1/rev1 by using the
FILE=>DIRECTORY menu.
VSIM> cd /xproj/ver1/rev1
4) Create the WORK directory: Select LIBRARY=>NEW and type WORK
VSIM> vlib work
5) Switch to VHDL’93 (use –93 in command line):
a) Click on VCOM
b) Click on the OPTIONS button and check “Use 1076-1993 language standard” and ACCEPT.
6) Compile VHDL File
a) Select TIME_SIM.VHD
b) Click on COMPILE
c) Select TSTATE_MCH2_GATE.VHD
d) Click on COMPILE
e) Close the VHDL Compiler window by clicking on DONE. The design is now ready for simulation.
VSIM>vcom –93 TIME_SIM.VHD
VSIM>vcom –93 TSTATE_MCH2_GATE.VHD
7) Start Simulation:
a) Click on VSIM
b) Click on Config CFG_TB_GUESSER
c) Select the SDF tab
SDF File: TIME_SIM.SDF
Apply to region: DUT
VSIM> vsim –sdftype DUT=time_sim.sdf cfg_tb_guesser
8) Simulate:
VSIM> view *
VSIM> wave *
VSIM> run 2000
9) Setup display: Windows=>Tile Horizontally
Synthesis Guide for ModelSim rev 1.0
11
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TGUESSER is
end TGUESSER;
architecture SIMULATE of TGUESSER is
component STATMCH2
port (
DATA, CLK, RST : in std_logic; -- Clock
GUESS : out std_logic); -- STATMCH2 result
end component;
constant CLK_PULSE : time := 50 ns;
signal TB_DATA,TB_RST,TB_CLK : std_logic;
signal TB_GUESS : std_logic;
begin
DUT: STATMCH2 port map( TB_DATA, TB_CLK, TB_RST, TB_GUESS );
TB_RST <= ’0’ after 0 ns,
’1’ after 50 ns,
’0’ after 100 ns;
TB_DATA <= ’0’ after 0 ns,
’1’ after 150 ns,
’0’ after 550 ns,
’1’ after 1000 ns;
--Create the clock
process (TB_RST, TB_CLK)
begin
if (TB_RST = ’1’ ) then
TB_CLK <= ’0’;
else
TB_CLK <= not TB_CLK after CLK_PULSE;
end if;
end process;
end SIMULATE;
-- Configuration for simulation
library WORK;
configuration CFG_TB_GUESSER of TGUESSER is
FOR SIMULATE
FOR DUT : STATMCH2
use entity work.STATMCH2(STRUCTURE);
END FOR;
END FOR;
END CFG_TB_GUESSER;
Figure 8: tstate_mch2_gate.vhd
Synthesis Guide for ModelSim rev 1.0