Отправлено AntZ 09 июня 2004 г. 12:58 В ответ на: вот такой простенький вопрос про PLL(+) отправлено Хом 09 июня 2004 г. 12:35

_PLL5502_Initialize:
		; Switch to bypass mode
		; Set bypass by setting PLLEN=0
		; Set PLL to reset by setting PLLRST=1
		; ***** PLLSCR ***** (PLL control/status register)
		;0000 0000 ~~~~ ~~~~ Reserved	R
		;~~~~ ~~~~ 0~~~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~1~~ ~~~~ STABLE		R	Oscillator output stable (1 -stable)
		;~~~~ ~~~~ ~~0~ ~~~~ LOCK		R	Lock mode indicator (1-PLL locked)
		;~~~~ ~~~~ ~~~0 ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~~ 1~~~ PLLRST		RW	Asserts reset on PLL (0 reset released)
		;~~~~ ~~~~ ~~~~ ~0~~ OSCPWRDN	RW	Sets internal Osc in powerdown mode (0 - osc is operational)
		;~~~~ ~~~~ ~~~~ ~~0~ PLLPWRDN	RW	Selects PLL powerdown (0 - PLL is operational)
		;~~~~ ~~~~ ~~~~ ~~~0 PLLEN		RW	PLL enable (0-bypass, 1-PLL)
		;0000 0000 0100 1000
		MOV		#0048h, port(#PLLCSR)
		
		; Set PLL multiplier
		; ***** PLLM ***** (PLL multiplier register)
		;0000 0000 000~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~0 1010 PLLM		RW	PLL multiplier select (1010 is 10)
		;0000 0000 0000 1010
		;MOV	#000Ah, port(#PLLM)		; 1010 - Clock*10
		MOV		#000Fh, port(#PLLM) 	; 1111 - Clock*15
		
		; Set PLL divider 0
		; This divider is before PLL
		
		; ***** PLLDIV0 ***** (PLL Divider 0 register)
		;1~~~ ~~~~ ~~~~ ~~~~ D0EN		RW	Divider D0 Enable
		;~000 0000 000~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~0 0000 PLLDIV0	RW	Divide ratio (0 - is divide by 1)
		;1000 0000 0000 0000
		MOV		#8000h, port(#PLLDIV0)
		; Set PLL divider 1
		; Fast peripherals group (DMA, HPI, Timers)
		; Divide by 2 (200/2=100Mhz)
		; ***** PLLDIV1 ***** (PLL Divider 1 register)
		;1~~~ ~~~~ ~~~~ ~~~~ D0EN		RW	Divider D1 Enable
		;~000 0000 000~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~0 0001 PLLDIV1	RW	Divide ratio (0 - is divide by 1)
		;1000 0000 0000 0001
		MOV	#8001h, port(#PLLDIV1)	; 1 -divide by 2
		; Set PLL divider 2
		; Slow peripherals group (McBSP, I2C, UART)
		; Divide by 4 (200/2=100Mhz)
		; ***** PLLDIV2 ***** (PLL Divider 2 register)
		;1~~~ ~~~~ ~~~~ ~~~~ D0EN		RW	Divider D2 Enable
		;~000 0000 000~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~0 0001 PLLDIV2	RW	Divide ratio (0 - is divide by 1)
		;1000 0000 0000 0001
		MOV	#8001h, port(#PLLDIV2)	; 1 -divide by 2
				
		; Set PLL divider 3
		; EMIF
		; Divide by 2 (200/2=100Mhz)
		; ***** PLLDIV3 ***** (PLL Divider 3 register)
		;1~~~ ~~~~ ~~~~ ~~~~ D0EN		RW	Divider D3 Enable
		;~000 0000 000~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~0 0001 PLLDIV3	RW	Divide ratio (0 - is divide by 1)
		;1000 0000 0000 0001
		MOV	#8001h, port(#PLLDIV3)	; 1 -divide by 2
		
		; Set OSCOUT divider
		; Internal oscilator is not used in this version
		; Divider is don't care
		; ***** OSCDIV1 ***** (OSC Divider register)
		;1~~~ ~~~~ ~~~~ ~~~~ D0EN		RW	Divider D2 Enable
		;~000 0000 000~ ~~~~ Reserved	R
		;~~~~ ~~~~ ~~~0 0011 PLLDIV2	RW	Divide ratio (0 - is divide by 1)
		;1000 0000 0000 0000
		MOV		#0000h, port(#OSCDIV1)
		; Wait 1ms as suggested by 5502 data manual
		; now a cycle is 1/20Mhz=50ns
		; CPU should wait at least 20 cycles
		RPT		#25
		NOP
		
		; Release PLL from reset
		;~~~~ ~~~~ ~~~~ 1~~~ PLLRST		RW	Asserts reset on PLL (0 reset released)
		AND		#~0008h, port(#PLLCSR)
		
		; Wait while PLL is acquiring phase lock
		; by polling LOCK bit of PLLCSR
		;~~~~ ~~~~ ~~0~ ~~~~ LOCK		R	Lock mode indicator (1-PLL locked)
loop:	MOV		port(#PLLCSR), T0
		AND		#0020h, T0
		BCC		loop, T0==#0
		
		; Switch to PLL operation mode
		;~~~~ ~~~~ ~~~~ ~~~0 PLLEN		RW	PLL enable (0-bypass, 1-PLL)
		OR		#0001h, port(#PLLCSR)
		RET